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Volumn , Issue , 2004, Pages 387-392

Circuit-based preprocessing of ILP and Its applications in leakage minimization and power estimation

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; COMPUTER SIMULATION; CONSTRAINT THEORY; GRAPH THEORY; INTEGER PROGRAMMING; LEAKAGE CURRENTS; LOGIC PROGRAMMING; MATHEMATICAL MODELS; OPTIMIZATION; RANDOM PROCESSES; VECTORS;

EID: 17644373135     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (15)
  • 2
    • 0030712582 scopus 로고    scopus 로고
    • A gate-level leakage power reduction method for ultra-low-power CMOS circuits
    • J. P. Halter and F. N. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," in IEEE Custom Integrated Circuits Conference, pp. 442-445, 1997.
    • (1997) IEEE Custom Integrated Circuits Conference , pp. 442-445
    • Halter, J.P.1    Najm, F.N.2
  • 3
    • 1542326846 scopus 로고    scopus 로고
    • Minimizing stand-by leaking power in static CMOS circuits
    • S. R. Naidu and E. Jacobs, "Minimizing stand-by leaking power in static CMOS circuits," in Design Automation and Test in Europe, pp. 370-376, 2001.
    • (2001) Design Automation and Test in Europe , pp. 370-376
    • Naidu, S.R.1    Jacobs, E.2
  • 4
    • 0026840166 scopus 로고
    • Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation
    • Mar.
    • S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation," IEEE Transactions on CAD, vol. 11, pp. 373-383, Mar. 1992.
    • (1992) IEEE Transactions on CAD , vol.11 , pp. 373-383
    • Devadas, S.1    Keutzer, K.2    White, J.3
  • 5
    • 0029358733 scopus 로고
    • Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations and their resolution
    • Aug.
    • H. Kriplani, F. Najm, and I. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations and their resolution," IEEE Transactions on CAD, vol. 14, pp. 998-1012, Aug. 1995.
    • (1995) IEEE Transactions on CAD , vol.14 , pp. 998-1012
    • Kriplani, H.1    Najm, F.2    Hajj, I.3
  • 7
    • 0042576426 scopus 로고
    • Applications de l'algebre de Boole en recherche operationelle
    • R. Fortet, "Applications de l'algebre de Boole en recherche operationelle," Revue Francaise de Recherche Operationelle, vol. 4, pp. 17-26, 1960.
    • (1960) Revue Francaise De Recherche Operationelle , vol.4 , pp. 17-26
    • Fortet, R.1
  • 8
    • 0029224152 scopus 로고
    • Verification of arithmetic circuits with binary moment diagrams
    • R. E. Bryant and Y.-A. Chen, "Verification of arithmetic circuits with binary moment diagrams," in Design Automation Conference, pp. 535-541, 1995.
    • (1995) Design Automation Conference , pp. 535-541
    • Bryant, R.E.1    Chen, Y.-A.2
  • 13
    • 0003934798 scopus 로고
    • SIS: A system for sequential circuit synthesis
    • UC Berkeley, May
    • E. Sentovich et al., "SIS: A system for sequential circuit synthesis," Tech. Rep. UCB/ERL M91/41, UC Berkeley, May 1992.
    • (1992) Tech. Rep. , vol.UCB-ERL M91-41
    • Sentovich, E.1
  • 15
    • 0031623626 scopus 로고    scopus 로고
    • Estimation of standby leakage power in cmos circuits considering accurate modeling of transistor stacks
    • Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in cmos circuits considering accurate modeling of transistor stacks," in International Symposium on Low Power Electronic Design, pp. 239-244, 1998.
    • (1998) International Symposium on Low Power Electronic Design , pp. 239-244
    • Chen, Z.1    Johnson, M.2    Wei, L.3    Roy, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.