Peak power estimation of VLSI circuits: New peak power measures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 4, 2000, Pages 435-439

  Hsiao, Michael S ^a   Rudnick, Elizabeth M ^b   Patel, James H ^b  

^a RUTGERS UNIVERSITY   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; RANDOM NUMBER GENERATION; SEMICONDUCTOR DEVICE MODELS; SEQUENTIAL CIRCUITS;

DELAY MODELS; FUNCTIONAL VECTOR LOOPS;

VLSI CIRCUITS;

EID: 0034245276     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.863624     Document Type: Article

References (15)

1. S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation," IEEE Trans. Computer-Aided Design, vol. 10, pp. 373-383, Mar. 1992.
2. H. Kriplani, "Worst case voltage drops in power and ground busses of CMOS VLSI circuits," Ph.D dissertation, Univ. Illinois, Urbana, IL, Nov. 1993.
3. H. Kriplani, F. Najm, P. Yang, and I. Hajj, "Resolving signal correlations for estimating maximum currents in CMOS combinational circuits," in Proc. Design Automation Conf., 1993, pp. 384-388.
4. S. Manne, A. Pardo, R. I. Bahar, G. D. Hachtel, F. Somenzi, E. Macii, and M. Poncino, "Computing the maximum power cycles of a sequential circuit," in Proc. Design Automation Conf., 1995, pp. 23-28.
5. C. Wang, K. Roy, and T. Chou, "Maximum power estimation for sequential circuits using a test generation based technique," in Proc. Custom Integrated Circuits Conf., 1996.
6. S. Manich and J. Figueras, "Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model," in Proc. Eur. Design and Test Conf., 1997, pp. 597-602.
7. Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of maximum power and instantaneous current using a genetic algorithm," in Proc. Custom Integrated Circuits Conf., 1997.
8. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison-Wesley, 1989.
9. P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout, and Test Automation. Englewood Cliffs, NJ: Prentice-Hall, 1999.
10. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: Computer Science, 1990.
11. T. M. Niermann and J. H. Patel, "HITEC: A test generation package for sequential circuits," in Proc. Eur. Conf. Design Automation (EDAC), 1991, pp. 214-218.
12. F. C. Hennie, Finite-State Models for Logical Machines. New York: Wiley, 1968.
13. C. Pixley, S.-W. Jeong, and G. D. Hachtel, "Exact calculation of synchronizing sequences based on binary decision diagrams," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1024-1034, Aug. 1994.
14. J. A. Wehbeh and D. G. Saab, "On the initialization of sequential circuits," in Proc. Int. Test Conf., 1994, pp. 233-239.
15. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "Effects of delay model in peak power estimation of VLSI sequential circuits," in Int. Conf. Computer-Aided Design, 1997, pp. 45-51.