Modeling the traffic effect for the application cores mapping problem onto NoCs

IFIP International Federation for Information Processing

Volumn 240, Issue , 2007, Pages 179-194

  Marcon, César A M ^a   Palma, José C S ^b   Calazans, Ney L V ^a   Moraes, Fernando G ^a   Susin, Altamiro A ^b   Reis, Ricardo A L ^b  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOAD FORECASTING; ENERGY UTILIZATION; MAPPING; MICROPROCESSOR CHIPS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPLEX NETWORKS; ENERGY CONSERVATION; PROGRAM COMPILERS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; TOPOLOGY;

APPLICATION MAPPING; APPLICATION MODELING; DYNAMIC ENERGY CONSUMPTION; HIGH LEVEL APPLICATIONS; NETWORK TRAFFIC; NETWORKS ON CHIPS; PACKET EXCHANGE; SYNTHETIC APPLICATION; MAPPING PROBLEM; SYSTEM ON A CHIP;

NETWORK-ON-CHIP;

EID: 34548753517     PISSN: 15715736     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-0-387-73661-7_12     Document Type: Conference Paper

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