Using rewriting logic to match patterns of instructions from a compiler intermediate form to coarse-grained processing elements

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Morra, Carlos ^a   Cardoso, João M P ^b   Becker, Jürgen ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b INESC ID   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CODES (SYMBOLS); OPTIMIZATION; PATTERN MATCHING; PROGRAM COMPILERS;

COARSE GRAINED PROCESSING ELEMENTS; PROCESSING ELEMENTS (PE); STATIC SINGLE ASSIGNMENT (SSA);

FORMAL LOGIC;

EID: 34548729608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370369     Document Type: Conference Paper

References (25)

1. K. Fan, M. Kudlur. H. Park, and S. Mahlke, "Compiler-directed Synthesis of Multifunction Loop Accelerators," in Workshop on Application Specific Processors (WASP), Sep. 2005, pp. 91-98.
2. R. Hartenstein, "A Decade of Reconfigurable Computing: a Visionary Retrospective," In Int'l Conf. on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-15, 2001, pp. 642-649.
3. S. S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, Inc., San Francisco, CA, USA, 1997.
4. R. Rodrigues, and João M. P. Cardoso, "On Pipelining Sequences of Data-Dependent Loops," in Journal of Universal Computer Science (JUCS), to appear.
5. J. M. P. Cardoso, "CHIADO: compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems," in SPIE Microtechnologies for the New Millennium 2005 Symposium, Seville, Spain, May 9-11, 2005, SPIE Vol. 5837, pp. 893-901.
6. H. Singh et al., "MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications," IEEE Trans. on Computers, Vol. 49, no. 5, May 2000, pp. 465-481.
7. B. Mei, A. Lambrechts, D. Verkest, J.Y.s Mignolet, R. Lauwereins, "Architecture Exploration for a Reconfigurable Architecture Template," in IEEE Design & Test of Computers, 22(2), 2005, pp. 90-101.
8. V. Baumgarte, et al., "PACT-XPP - A Self-reconfigurable Data Processing Architecture," In Journal of Supercomputing, Kluwer Academic Publishers, vol. 26, issue. 2, September 2003, pp. 167-184.
9. M. D. Galanis, G. Theodoridis, S. Tragoudas, C. E. Goutis, "A High Performance Data-Path for Synthesizing DSP Kernels," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 6, June 2006, pp. 1154-1163.
10. F. Baader, and T. Nipkow. Term Rewriting and All That. Cambridge University Press, 1998.
11. P. Borovansky, C. Kirchner, H. Kirchner, and P. Moreau, "ELAN from a rewriting logic point of view," Theoretical Computer Science, vol. 285, no. 2, 2002.
12. M. Clavel, F. Durán, S. Eker, P. Lincoln, N. Martí-Oliet, J. Meseguer and C. Talcott. "The Maude 2.0 System" in Rewriting Techniques and Applications (RTA 2003), LNCS 2706, Springer-Verlag, June 2003, pp. 76-87.
13. J. Meseguer, N. Martí-Oliet and A.Verdejo. "Towards a strategy language for Maude" in Proc. Fifth Int'l Workshop on Rewriting Logic and its Applications (WRLA 2004), Electronic Notes in Theoretical Computer Science, Elsevier, 2004.
14. J. M. P. Cardoso, and M. Weinhardt, "XPP-VC: A C compiler with temporal partitioning for the PACT-XPP architecture," in Proc. 12th Int'l Conf. on Field-Programmable Logic and Applications (FPL '02), 2002.
15. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, "DRESC: A retargetable compiler for coarse-grained reconfigurable architectures," in Proc. Int'l Conference on Field Programmable Technology (FPL '02), 2002.
16. R. W. Hartenstein, M. Herz, T. Hoffmann, and U. Nageldinger, "KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array," in Proc. ASP-DAC, vol. 1, 2000, pp. 163-168.
17. H. Park, K. Fan, M. Kudlur, and S. Mahlke, "Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures," in Proc. Int'l Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'06), Oct. 2006.
18. N. Clark, H. Zhong, and S. Mahlke, "Automated Custom Instruction Generation for Domain-Specific Processor Acceleration," in IEEE Transactions on Computers, Vol. 54, No. 10, Oct. 2005, pp. 1258-1270.
19. R. Kastner, A. Kaplan, S. Ogrenci Memik, and E. Bozorgzadeh "Instruction generation for hybrid reconfigurable systems," in ACM Trans. Design Autom. Electr. Syst. (TODAES), 7(4), 2002, pp. 605-627.
20. M. Ayala-Rincón, Carlos Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein, "Prototyping Time and Space Effiicient Computations of Algebraic Operations over Dynamically Reconfigurable Systems Modeled by Rewriting-Logic," in ACM Transactions On Design Automation Of Electronic Systems (TODAES), vol. 11, no. 2, 2006, pp. 251-281.
21. D. Kapur and M. Subramaniam, "Using and induction prover for verifying arithmetic circuits," Journal of Software Tools for Technology Transfer, vol. 3, no. 1, pp. 32-65, Sept. 2000.
22. Arvind and X. Shen, "Using term rewriting systems to design and verify processors," IEEE Micro, vol. 19, no. 3, 1999, pp. 36-46.
23. M. Ayala-Rincon, R. Jacobi, L. Carvalho, C. Llanos, and R. Hartenstein, "Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic," in Proc. SBCCI'04, 2004.
24. C. Morra, J. Becker, M. Ayala-Rincon, R. Hartenstein, "FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations" in Proc. 15th Int'l Conference on Field-Programmable Logic and Applications (FPL'05), Aug. 24 - 26, 2005, Tampere, Finland.
25. C. Morra, M. Sackmann, S. Shukla, J. Becker, R. Hartenstein. "From Equation to VHDL: Using Rewriting Logic For Automated Function Generation," in 16th Int'l Conference on Field-Programmable Logic and Applications (FPV'06), Aug. 28 - 30, 2006, Madrid, Spain.