From equation to VHDL: Using rewriting logic for automated function generation

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 679-682

  Morra, C ^a   Sackmann, M ^a   Shukla, S ^b   Becker, J ^a   Hartenstein, R ^c  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b UNIVERSITY OF QUEENSLAND   (Australia)

^c University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; EQUIVALENCE CLASSES; FUNCTION EVALUATION; FUZZY LOGIC; INFORMATION THEORY; POLYNOMIALS;

ALGEBRAIC EXPRESSIONS; AUTOMATED GENERATION; CONTINUOUS FUNCTIONS; DESIGN FLOWS; FIELD PROGRAMMABLE LOGIC (FPL); FUNCTION GENERATION; GENERATING POLYNOMIAL; HARDWARE SYNTHESIS; INTERNATIONAL CONFERENCES; LEVEL OF ABSTRACTION; LEVELS OF ABSTRACTION (LOA); MATHEMATICAL EQUATIONS; NUMBER REPRESENTATIONS; PARAMETERIZED; POLYNOMIAL DEGREES; POLYNOMIAL EVALUATIONS; POLYNOMIAL GENERATION; REWRITING LOGIC (RWL); TOOL-FLOW;

POLYNOMIAL APPROXIMATION;

EID: 46249121085     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311289     Document Type: Conference Paper

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