Conserving memory bandwidth in chip multiprocessors with runahead execution

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Karlsson, Martin ^a   Hagersten, Erik ^a  

^a UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COST EFFECTIVENESS; MICROPROCESSOR CHIPS;

CHIP MULTIPROCESSORS (CMPS); MEMORY LATENCIES; RUNAHEAD EXECUTION;

INTERCONNECTION NETWORKS;

EID: 34548705323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370234     Document Type: Conference Paper

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