Accurate temperature-dependent integrated circuit leakage power estimation is easy

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1526-1531

  Yongpan, Liu ^a   Dick, Robert P ^b   Shang, Li ^c   Huazhong, Yang ^a  

^a TSINGHUA UNIVERSITY   (China)

^b NORTHWESTERN UNIVERSITY   (United States)

^c QUEEN S UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; MATHEMATICAL MODELS; TEMPERATURE DISTRIBUTION; TEMPERATURE MEASUREMENT;

LINEAR MODELS; OPERATING TEMPERATURES; THERMAL PROFILE;

INTEGRATED CIRCUITS;

EID: 34548358706     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364517     Document Type: Conference Paper

References (24)

1. "International Technology Roadmap for Semiconductors," 2005, http://public.itrs.net.
2. S. Naffziger, et ai., "The implementation of a 2-core, multi-threaded itanium family processor," J. Solid-State Circuits, vol. 41, no. 1, pp. 197-209, Jan. 2006.
3. J. A. Butts and G. S. Sohi, "A static power model for architects," in Proc. Int. Symp. Microarchitecture, Dec. 2000, pp. 191-201.
4. S. M. Martin, et al., "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 721-725.
5. S. Narendra, et al., "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18 CMOS," J. Solid-State Circuits, vol. 39, no. 2, pp. 501-510, Feb. 2004.
6. Y. F. Tsai, et al., "Characterization and modeling of run-time techniques for leakage power reduction," IEEE Trans. VLSI Systems, vol. 12, no. 11, pp. 1221-1232, Nov. 2004.
7. A. Abdollahi, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," IEEE Trans. VLSI Systems, vol. 12, no. 2, pp. 140-154, Feb. 2004.
8. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
9. Y. Zhang, et al., "HotLeakage: A temperature-aware model of subthresh-old and gate leakage for architects," Univ. of Virginia, Tech. Rep., May 2003, CS-2003-05.
10. H. Su, et al., "Full chip leakage estimation considering power supply and temperature variations," in Proc. Int. Symp. Low Power Electronics & Design, Aug. 2003, pp. 78-83.
11. W. P. Liao, L. He, and K. M. Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1042-1053, July 2005.
12. A. Chandrakasan, W. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits. IEEE Press, 2001.
13. K. M. Cao, et al., "BSIM4 gate leakage model including source-drain partition," in IEDM Technology Dig., Dec. 2000, pp. 815-818.
14. "ISCAS85 benchmarks suite," http://www.visc.vt.edu/~mhsiao/ iscas85.html.
15. F. Zhang, "System-level leakage power modeling methodology," Dept. of Electronics Engg., Tsinghua University," Bachelor's Degree Thesis, July 2006.
16. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45nm design exploration," in Proc. Int. Symp. Quality of Electronic Design, Mar. 2006, pp. 585-590.
17. G. S. Ohm, "The Galvanic circuit investigated mathematically," 1827.
18. J. Fourier, The Analytical Theory of Heat, 1822.
19. K. Skadron, et al., "Temperature-aware microarchitecture," in Proc. Int. Symp. Computer Architecture, June 2003, pp. 2-13.
20. W. Huang, et al., "HotSpot: A compact thermal modeling methodology for early-stage VLSI design," IEEE Trans. VLSI Systems, vol. 14, no. 5, pp. 501-524, May 2006.
21. I. C. Kuon, "Automated FPGA design verification and layout," Ph.D. dissertation, Dept. of Electrical and Computer Engg., University of Toronto, July 2004.
22. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proc. Int. Symp. Computer Architecture, June 2000, pp. 83-94.
23. "SRAM layout," SRAM link at http://www.eecs.umich.edu/UMichMP/ Presentations.
24. "MCNC benchmarks suite," http://www.cse.ucsc.edu/research/surf/ GSRC/MCNCbench.html.