Layout-aware gate duplication and buffer insertion

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1367-1372

  Baneres D ^a   Cortadella, J ^a   Kishinevsky, M ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

BUFFER INSERTION; COMBINATORIAL EXPLOSION; INTERCONNECT OPTIMIZATION;

GATES (TRANSISTOR);

EID: 34548354623     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364488     Document Type: Conference Paper

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