Efficient global fanout optimization algorithms

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 571-576

  Murgai, R ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Algorithm design and analysis; Capacitance; Circuits; Constraint optimization; Delay effects; Design optimization; Laboratories; Logic; Pins; Timing

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER AIDED DESIGN; CONSTRAINED OPTIMIZATION; DELAY CIRCUITS; DESIGN; LABORATORIES; NETWORKS (CIRCUITS); TIMING CIRCUITS;

ALGORITHM DESIGN AND ANALYSIS; CONSTRAINT OPTIMIZATIONS; DELAY EFFECTS; DESIGN OPTIMIZATION; LOGIC; PINS; TIMING;

OPTIMIZATION;

EID: 34548332820     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913369     Document Type: Conference Paper

References (9)

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