Simultaneous timing-driven placement and duplication

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2005, Pages 51-59

  Chen, Gang ^a   Gong, Jason ^b  

^a MAGMA DESIGN AUTOMATION   (United States)

^b Engineering IV   (United States)

Author keywords

FPGA; Legalization; Logic duplication; Redundancy removal; Timing driven placement

Indexed keywords

ALGORITHMS; DATA REDUCTION; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; RECURSIVE FUNCTIONS; REDUNDANCY;

DELAY OPTIMIZATION; LEGALIZATION; LOGIC DUPLICATION; REDUNDANCY REMOVAL; TIMING-DRIVEN PLACEMENT;

LOGIC DEVICES;

EID: 20344394204     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1046192.1046200     Document Type: Conference Paper

References (14)

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