Timing Driven Gate Duplication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 1, 2004, Pages 42-51

  Srivastava, Ankur ^a   Kastner, Ryan ^b   Chen, Chunhong ^c   Sarrafzadeh, Majid ^d  

^a UNIVERSITY OF MARYLAND   (United States)

^b University of California   (United States)

^c UNIVERSITY OF WINDSOR   (Canada)

^d Engineering IV   (United States)

Author keywords

Delay optimization; Gate duplication; Logic synthesis

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PROBLEM SOLVING;

DELAY OPTIMIZATION; GATE DUPLICATION; LOGIC SYNTHESIS;

LOGIC GATES;

EID: 1342329329     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.820527     Document Type: Article

References (31)

1. A. Saldanha, H. Harkness, P. C. McGeer, R. K. Brayton, and A. L. S. Vincentelli, "Performance optimization using exact sensitization," in Proc Design Automation Conf., June 1994, pp. 425-429.
2. A. Salek, J. Lou, and M. Pedram, "A DSM design flow: Putting floor-planning, technology mapping and gate placement together," in Proc Design Automation Conf., June 1998, pp. 287-290.
3. _, "A simultaneous routing tree construction and fanout optimization algorithm," in Proc Int. Conf. Computer-Aided Design, Nov. 1998, pp. 625-630.
4. A. Srivastava, C. Chen, and M. Sarrafzadeh, "Timing driven gale duplication in technology independent phase," in Proc. Asia South Pacific Design Automation Conf., Jan. 2001, pp. 577-582.
5. A. Srivastava, R. Kastner, and M. Sarrafzadeh, "On the complexity of gate duplication," IEEE Trans. Computer-Aided Design, Sept. 2001, to be published.
6. _, "Complexity issues in gate duplication," in Workshop Notes, International Workshop on Logic Synthesis, May 2000.
7. _, "On the Complexity of Gate Duplication, Internal Report," ER-Lab, Univ. California, Los Angeles, 2000.
8. _, "Timing driven gate duplication: Complexity issues and algorithms," in Proc. Int. Conf. Computer-Aided Design, Nov. 2000.
9. C. Chen and C. Tsui, "Timing optimization of logic network using gate duplication," in Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 233-236.
10. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Department of EECS, Univ. of California, Berkeley, Memorandum no. UCB/ERL M92/41, 1992.
11. H. Vaishnav and M. Pedram, "Routability driven fanout optimization," in Proc Design Automation Conf., June 1993, pp. 230-235.
12. I. Neumann, D. Stoffel, H. Hartje, and W. Kunz, "Cell replication and redundancy elimination during placement for cycle time optmization," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 25-30.
13. J. Darringer, D. Brand, J. Gerbi, W. Joyner, and L. Trevillyan, "LSS: A system for production logic synthesis," IBM J. Res. Develop., vol. 28, no. 5, pp. 326-328, Sept. 1985.
14. J. Lou, A. Salek, and M. Pedram, "An exact solution to simultaneous technology mapping and linear placement problem," in Proc Int. Conf. Compute-Aided Design, Nov. 1997, pp. 671-675.
15. K. Bartlett, W. Cohen, A. J. De Geus, and G. D. Hachtel, "Synthesis of multi-level logic under timing constraints," IEEE Trans. Computer-Aided Design, October 1986.
16. K. C. Chen and S. Muroga, "Timing optimization for multilevel combinational networks," in Proc Design Automation Conf., June 1990, pp. 339-344.
17. K. J. Singh, A. R. Wang, R. K. Brayton, and A. L. S. Vincentelli, "Timing optimization of combinational logic," in Proc. Int. Conf. Computer-Aided Design, Nov. 1988, pp. 282-285.
18. C. Kring and A. R. Newton, "A cell replication approach to mincut-based circuit partitioning," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 2-5.
19. L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal elmore delay," in Proc Int. Symp. Circuits and Systems, Dec. 1990, pp. 865-868.
20. M. Enos, S. Hauck, and M. Sarrafzadeh, "Evaluation and optimization of replication algorithms for logic bipartitioning," IEEE Trans. Computer-Aided Design, pp. 1237-1248, Sept. 1999.
21. M. Pedram and N. Bhat, "Layout driven logic restructuring/decomposition," in Proc Int. Conf. Computer-Aided Design, Nov. 1991, pp. 134-137.
22. _, "Layout driven technology mapping," in Proc Design Automation Conf., June 1991, pp. 99-105.
23. G. De Micheli, "Performance oriented synthesis of large-scale domino CMOS circuits," IEEE Trans. Computer-Aided Design, pp. 751-765, Sept. 1987.
24. R. Murgai, "On the global fanout optimization problem," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 511-515.
25. O. Coudert, R. Haddad, and S. Manne, "New algorithms for gate sizing: A comparative study," in Proc Design Automation Conf., June 1996, pp. 734-739.
26. P. Chan, "Algorithms for library specific sizing of combinational circuits," in Proc Design Automation Conf., June 1990, pp. 353-356.
27. R. Carragher, R. Murgai, S. Chakraborty, M. R. Prasad, A. Srivastava, and N. Vemuri, "Layout driven logic optimization," presented at the Proc. Workshop Handouts, International Workshop on Logic Synthesis, Dana Pt., CA, May 2000.
28. R. K. Brayton, G. D. Hachtel, and A. L. S. Vincentelli, "Multilevel logic synthesis," Proc IEEE, vol. 78, no. 2, pp. 264-300, Feb. 1990.
29. T. Okamoto and J. Cong, "Interconnect layout optimization by simultaneous steiner tree construction and buffer insertion," in Proc. ACM/SIGDA Physical Design Workshop, 1996, pp. 1-6.
30. H. Touati, "Performance Oriented Technology Mapping," Ph.D. dissertation, Univ. of Calif., Berkeley, 1990.
31. Y. Jiang and S. Sapatnekar, "An integrated algorithm for combined placement and libraryless technology mapping," in Proc Int. Conf. Computer-Aided Design, Nov. 1999, pp. 102-105.