Techniques for improved placement-coupled logic replication

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 211-216

  Kim, Hosung ^a   Lillis, John ^a   Hrkić, Miloš ^b  

^a University of Illinois at Chicago   (United States)

^b IBM   (United States)

Author keywords

Logic replication; Placement; Programmable logic; Timing optimization

Indexed keywords

CIRCUIT THEORY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; TIMING CIRCUITS;

LOGIC REPLICATION; PROGRAMMABLE LOGIC; TIMING OPTIMIZATION;

LOGIC CIRCUITS;

EID: 33750910360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127959     Document Type: Conference Paper

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