On the complexity of gate duplication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 9, 2001, Pages 1170-1176

  Srivastava, A ^a   Kastner, R ^a   Sarrafzadeh, M ^a  

^a Engineering IV   (United States)

Author keywords

Gate duplication; NP completeness; Required time; Satisfiability; VLSI

Indexed keywords

COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; DELAY CIRCUITS; GLOBAL OPTIMIZATION; MATHEMATICAL MODELS; PROBLEM SOLVING; VLSI CIRCUITS;

GATE DUPLICATION;

GATES (TRANSISTOR);

EID: 0035440959     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.945312     Document Type: Article

References (9)

1. Timing driven gate duplication in technology independent phase
2. Complexity issues in gate duplication
3. Timing driven gate duplication: Complexity issues and algorithms
4. Timing optimization of logic network using gate duplication
5. Design and analysis of physical design algorithms
6. On the global fan-out optimization problem
7. Performance optimization under rise and fall parameters