AsAP: A fine-grained many-core platform for DSP applications

IEEE Micro

Volumn 27, Issue 2, 2007, Pages 34-45

  Baas, Bevan ^a   Yu, Zhiyi ^a   Meeuwsen, Michael ^a   Sattari, Omar ^a   Apperson, Ryan ^a   Work, Eric ^a   Webb, Jeremy ^a   Lai, Michael ^a   Mohsenin, Tinoosh ^a   Truong, Dean ^a   Cheung, Jason ^a  

^a University of California   (United States)

Author keywords

Digital signal processing; Embedded systems; GALS networking; Microarchitecture; MIMD processors; Multiprocessors; Special purpose and application based systems

Indexed keywords

DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

FINE-GRAINED MANY-CORE PLATFORM; MICROARCHITECHTURE;

MULTIPROCESSING SYSTEMS;

EID: 34548224613     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.29     Document Type: Conference Paper

References (20)

1. S. Agarwala et al., "A 600-MHz VLIW DSP," J. Solid-State Circuits vol. 37, no. 11, Nov. 2002, pp. 1532-1544.
2. Z. Yu and B.M. Baas, "Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems," Proc. IEEE Computer Soc. Ann. Symp. Emerging VLSI Technologies and Architectures (ISVLSI 06), IEEE CS Press, 2006, pp. 378-384.
3. Z. Yu et al., "An Asynchronous Array of Simple Processors for DSP Applications," Proc. Int'l Solid-State Circuits Conf. (ISSCC 06), IEEE Press, 2006, pp. 428-429.
4. M. Taylor et al., "A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network," Proc. Int'l Solid-State Circuits Conf. (ISSCC 03), IEEE Press, 2003, pp. 170-171.
5. A. Suga et al., "A 4-Way VLIW Embedded Multimedia Processor," Proc. Int'l Solid-State Circuits Conf. (ISSCC 00), IEEE Press, 2000, pp. 240-241.
6. A.A. Bright et al., "Creating the BlueGene/L Supercomputer from Low-Power SoC ASICs," Proc. Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, pp. 188-189.
7. B. Flachs et al., "A Streaming Processing Unit for a CELL Processor," Proc. Int'l Solid-State Circuits Conf. (ISSCC 05, IEEE Press, 2005, pp. 134-135.
8. R. Witek and J. Montanaro, "StrongARM: A High-Performance ARM Processor," Proc. IEEE Int'l Computer Conf. (Compcon 96), IEEE CS Press, 1996, pp. 188-191.
9. C. Kozyrakis and D. Patterson, "Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks," Proc. IEEE/ACM Int'l Symp. Microarchitecture (Micro 35), IEEE CS Press, 2002, pp. 283-289.
10. T. Lin and C. Jen, "Cascade - Configurable and Scalable DSP Environment," Proc. Int'l Symp. Circuits and Systems (ISCAS 02), IEEE Press, 2002, pp. 26-29.
11. M.J. Meeuwsen, O. Sattari, and B.M. Baas, "A Full-Rate Software Implementation of an IEEE 802.11 a Compliant Digital Baseband Transmitter," Proc. IEEE Workshop Signal Processing Systems (SIPS 04), IEEE Press, 2004, pp. 124-129.
12. M.F. Tariq et al., "Development of an OFDM Based High Speed Wireless LAN Platform Using the TI C6x DSP," Proc. IEEE Int'l Conf. Comm. (ICC 02), vol. 1, IEEE Press, 2002, pp. 522-526.
13. B.M. Baas, "A Parallel Programmable Energy-Efficient Architecture For Computationally-Intensive DSP Systems," Conf. Record 37th Asilomar Conf. Signals, Systems, and Computers, IEEE Press, 2003, pp. 2185-2189.
14. C. Whitby-Strevens, "Transputers - Past, Present and Future," IEEE Micro, vol. 10, no. 6, Nov.-Dec. 1990, pp. 16-19, 76-82.
15. H.T. Kung, "Why Systolic Architecture?" Computer, vol. 15, no. 1, Jan. 1982, pp. 37-46.
16. S.Y. Kung et al., "Wavefront Array Processor: Language, Architecture, and Applications," IEEE Trans. Computers, vol. 31, no. 11, Nov. 1982, pp. 1054-1066.
17. R.A. Sutton, V.P. Srini, and J.M. Rabaey, "A Multiprocessor DSP System using PADDI-2," Proc. 35th Design Automation Conf. (DAC 98), ACM Press, 1998, pp. 62-65.
18. J. Oliver et al., "Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor," Proc. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 150-161.
19. R. Baines and D. Pulley, "A Total Cost Approach to Evaluating Different Reconfigurable Architecture Architectures for Baseband Processing in Wireless Receivers," IEEE Comm. Magazine, vol. 41, no. 1, Jan. 2003, pp. 105-113.
20. Multiprocessor DSPs: Next Stage in the Evolution of Media Processor DSPs, tech. report, Cradle Technologies; http://www. ed-china.com/ ARTICLES/2006MAY/5/2006MAY29_CP_EMS_TS_1.PDF.