Device technology for body biasing scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 13-16

  Imai, Kiyotaka ^a   Yamagata, Yasushi ^a   Masuoka, Sadaaki ^a   Kimuzuka, Naohiko ^a   Yasuda, Yuri ^a   Togo, Mitsuhiro ^a   Ikeda, Masahiro ^a   Nakashiba, Yasutaka ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

65-NM NODE; BODY BIAS; BODY BIASING; CMOS DEVICES; DEVICE RELIABILITY; DEVICE TECHNOLOGIES; GATE LEAKAGES; GATE LENGTH; HIGH-K GATE DIELECTRICS; HIGH-PERFORMANCE CMOS; LOW STAND-BY POWER; POWER SUPPLY; POWER-AWARE; STAND-BY LEAKAGE;

ELECTRIC POTENTIAL; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; VOLTAGE REGULATORS;

GATE DIELECTRICS;

EID: 34248401759     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464512     Document Type: Conference Paper

References (6)

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