Heavy ion energy effects in CMOS SRAMs

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 889-893

  Dodd, P E ^a   Schwank, J R ^a   Shaneyfelt, M R ^a   Ferlet Cavrois, V ^b   Paillet, P ^b   Baggio, J ^b   Hash, G L ^a   Felix, J A ^a   Hirose, K ^c   Saito, H ^c  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b CEA DIF   (France)

^c Space and Astronautical Science ^*  (Japan)

Author keywords

Indirect ionization; Integrated circuit reliability; Nuclear reactions; Radiation effects; Radiation hardness assurance; Single event effects; Single event latchup; Single event upset

Indexed keywords

CMOS INTEGRATED CIRCUITS; HARDNESS; HEAVY IONS; IONIZATION; RADIATION EFFECTS; RADIATION HARDENING;

HEAVY ION TESTING; INTEGRATED CIRCUIT RELIABILITY; RADIATION HARDNESS ASSURANCE; SINGLE EVENT EFFECTS; SINGLE EVENT LATCHUP; SINGLE EVENT UPSET;

STATIC RANDOM ACCESS STORAGE;

EID: 34548086952     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.893425     Document Type: Conference Paper

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