Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 9, 2007, Pages 990-1002

  Joshi, Ajay J ^a,b   Lopez, Gerald G ^a,c   Davis, Jeffrey A ^a,c  

^a IEEE

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Low power high performance design; On chip interconnects; On chip networks; Time division multiplexing (TDM); Wave pipelined multiplexing (WPM)

Indexed keywords

MICROPROCESSOR CHIPS; NETWORK ROUTING; OPTIMIZATION; TIME DIVISION MULTIPLEXING; VLSI CIRCUITS;

LOW-POWER HIGH-PERFORMANCE DESIGN; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; WAVE-PIPELINED MULTIPLEXING (WPM);

INTERCONNECTION NETWORKS;

EID: 34548082737     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.902209     Document Type: Article

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