Energy reduction through crosstalk avoidance coding in NoC paradigm

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 689-695

  Pande, Partha Pratim ^a   Haibo, Zhu ^a   Ganguly, Amlan ^a   Grecu, Cristian ^b  

^a Washington State University   (United States)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Crosstalk; Crosstalk avoidance codes; Interconnect energy; Networks on chip; Wormhole switching

Indexed keywords

COMPUTER ARCHITECTURE; CROSSTALK; EMBEDDED SYSTEMS; MULTIPROCESSING SYSTEMS; PACKET NETWORKS; SIGNAL ENCODING;

CROSSTALK AVOIDANCE CODES; INTERCONNECT ENERGY; NETWORKS ON CHIPS; WORMHOLE SWITCHING;

MICROPROCESSOR CHIPS;

EID: 34547998120     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.49     Document Type: Conference Paper

References (16)

1. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78
2. P. Magarshack and P.G. Paulin, "System-on-Chip beyond the Nanometer Wall," Proc. 40th Design Automation Conf. (DAC 03), ACM Press, 2003, pp. 419-424.
3. R. Ho, K. W. Mai, M.A. Horowitz, "The Future of Wires", Proceedings of the IEEE, Volume: 89 Issue: 4, April 2001 pp. 490-504
4. A. Jantsch, H. Tenhunen (Eds.), Networks on Chip, Kluwer Academic Publishers, 2003
5. S. R. Sridhara, and N. R. Shanbhag "Coding for System-on-Chip Networks: A Unified Framework", IEEE transactions on very large scale integration (VLSI) systems, vol. 13, no. 6, June 2005, pp. 655-667
6. C. Grecu, P. P. Pande, A. Ivanov, R. Saleh, "Timing Analysis of Network on Chip Architectures for MP-SoC Platforms", Microelectronics Journal, Elsevier, Vol. 36, issue 9, pp. 833-845.
7. V. Raghunathan, M. B. Srivastava, R. K. Gupta, "A Survey of Techniques for Energy Efficient on-chip Communications", Proceedings of Design, Automation and Test in Europe (DATE), Munich, Germany, June 2003, pp. 900-905
8. M. R. Stan and W. P. Burleson, "Low-power encodings for global communication in CMOS VLSF', IEEE transactions on very large scale integration (VLSI) systems, Volume 5, Issue 4, Dec. 1997 pp:444 - 455
9. C. Kretzschmar, A. K. Nieuwland, D. Muller, "Why Transition Coding for Power Minimization of on-Chip Buses does not work", Proceedings of the Design, Automation and Test in Europe Conference and Exhibition,(DATE), 16-20 Feb. 2004 pp. 512-517
10. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, "Performance Evaluation and Design Trade-offs for Network on Chip Interconnect Architectures", IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025-1040, August 2005.
11. V. Soteriou and L. S. Peh, "Design-space exploration of power-aware on/off interconnection networks", Proceedings of IEEE International Conference on Computer Design (ICCD), 11-13 Oct. 2004, pp:510-517
12. th International Symposium on High Performance Computer Architecture (HPCA-9), 8-12 Feb. 2003, pp.91 - 102
13. Open Core Protocol, www.ocpip.org.
14. AMBA Bus specification, http://www.arm.com.
15. P. P. Sotiriadis and A. P. Chandrakasan, "A bus energy model for deep submicron technology", IEEE transactions on very large scale integration (VLSI) systems, Volume 10, Issue 3, June 2002, pp. 341-350
16. S. R. Sridhara, and N. R. Shanbhag, "Coding for reliable onchip buses: fundamental limits and practical codes", Proceedings of IEEE International Conference on VLSI Design, 3-7 Jan 2005, pp. 417-422