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Volumn , Issue , 2006, Pages 537-544

Layered decoding of non-layered LDPC codes

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER ARCHITECTURE; CONVERGENCE OF NUMERICAL METHODS; PROBLEM SOLVING; ROBUSTNESS (CONTROL SYSTEMS);

EID: 34547993277     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.63     Document Type: Conference Paper
Times cited : (41)

References (22)
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    • A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder
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    • Chen, Y.1    Hocevar, D.2
  • 5
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    • A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 Turbo Gallager code decoder
    • Aug-Sept
    • P. Ciao, G. Colavolpe, and L. Fanucci. A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 Turbo Gallager code decoder. In Euromicro Symposium on Digital System Design (DSD), pages 174-181, Aug-Sept. 2004.
    • (2004) Euromicro Symposium on Digital System Design (DSD) , pp. 174-181
    • Ciao, P.1    Colavolpe, G.2    Fanucci, L.3
  • 6
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    • 17044383428 scopus 로고    scopus 로고
    • A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes
    • D. Hocevar. A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes. In IEEE Workshop on Signal Processing Systems, SISP 2004, pages 107-112, 2004.
    • (2004) IEEE Workshop on Signal Processing Systems, SISP 2004 , pp. 107-112
    • Hocevar, D.1
  • 8
    • 17944400187 scopus 로고    scopus 로고
    • Efficient implementations of the sum-product algorithm for decoding LDPC codes
    • Nov
    • X.-Y. Hu, E. Eleftheriou, D.-M. Arnold, and A. Dholakia. Efficient implementations of the sum-product algorithm for decoding LDPC codes. In Proc. IEEE GLOBECOM, volume 2, pages 1036-1036E, Nov 2001.
    • (2001) Proc. IEEE GLOBECOM , vol.2
    • Hu, X.-Y.1    Eleftheriou, E.2    Arnold, D.-M.3    Dholakia, A.4
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    • Parallel versus sequential updating for belief propagation decoding
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    • V. Nagarajan, N. Jayakumar, S. Khatri, and O. Milenkovic. High-throughput VLSI implementations of iterative decoders and related code construction problems. In Proc. IEEE Global Telecommun. Conf., pages 361-365, Nov-Dec 2004.
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    • A. Vila Casado, W. W., and R. Wesel. Multiple rate low-density parity-check codes with constant block length. In Asilomar Conf. on Signals, Systems and Computers, 2, pages 2010-2014, Nov 2004.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.