Overview and future challenge of ferroelectric random access memory technologies

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 46, Issue 4 B, 2007, Pages 2157-2163

  Kato, Yoshihisa ^a   Kaneko, Yukihiro ^a   Tanaka, Hiroyuki ^a   Kaibara, Kazuhiro ^a   Koyama, Shinzo ^a   Isogai, Kazunori ^a   Yamada, Takayoshi ^a   Shimada, Yasuhiro ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

Bi4Ti 3O12; Design productivity; Ferroelectric random access memory; Nondestructive readout operation; Power consumption; Security; SrBi2Ta2O9

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FABRICATION; NONDESTRUCTIVE EXAMINATION; RANDOM ACCESS STORAGE; READOUT SYSTEMS;

DESIGN PRODUCTIVITY; FERROELECTRIC RANDOM ACCESS MEMORY; NONDESTRUCTIVE READOUT OPERATION;

FERROELECTRIC MATERIALS;

EID: 34547924166     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.46.2157     Document Type: Article

References (21)

1. C. A. Paz de Araujo, J. D. Cuchiaro, L. D. McMillan, M. C. Scott, and J. F. Scott: Nature 374 (1995) 627.
2. A. J. Menezes, P. C. van Oorschot, and S. A. Vanstone: Handbook of Applied Cryptography (CRC Press, Boca Raton, 1996) Chap. 1.
3. Y. Taur: IBM. J. Res. Dev. 46 (2002) 213.
4. The International Technology Roadmap for Semiconductors (http://public.itrs.net/, 2005) Chap. Design.
5. O. Kömmerling and M. G. Kuhn: Proc. USENIX Workshop Smartcard Technology, 1999, p. 9.
6. Y. Nagano, T. Mikawa, T. Kutsunai, S. Natsume, T. Tatsunari, T. Ito, A. Noma, T. Nasu, S. Hayashi, H. Hirano, Y. Gohou, Y. Judai, and E. Fujii: IEEE Trans. Semicond. Manuf. 18 (2005) 49.
7. S. Koyama, Y. Kato, T. Yamada, and Y. Shimada: IEICE Trans. Electron. E89-C (2006) 1368.
8. T. Ninomiya, S. Masui, M. Oura, K. Mukaida, and T. Teramoto: Tech. Rep. IEICE SDM2002-268 (2003) p. 25 [in Japanese].
9. T. Miwa, J. Yamada, H. Koike, T. Nakura, T. Kobayashi, N. Kasai, and H. Toyoshima: Symp. VLSI Technology Dig. Tech. Pap., 2001, p. 129.
10. M. Motomura: presented at Microprocessor Forum, 2002.
11. S. Masui, T. Ninomiya, M. Oura, W. Yokozeki, K. Mukaida, and S. awashima: Symp. VLSI Technology Dig. Tech. Pap., 2001, p. 200.
12. Md. R. Anisur, T. Osipowicz, D. Z. Chi, and W. D. Wang: J. Electron. Mater. 34 (2005) 1110.
13. T. Osaka, A. Sakakibara, T. Seki, S. Ono, I. Koiwa, and A. Hashimoto: Jpn. J. Appl. Phys. 37 (1998) 597.
14. T. Kijima, M. Ushikubo, and H. Matsunaga: Jpn. J. Appl. Phys. 38 (1999) 127.
15. M. Yamada, N. Iizawa, T. Yamaguchi, W. Sakamoto, K. Kikuta, T. Yogo, T. Hayashi, and S. Hirano: Jpn. J. Appl. Phys. 42 (2003) 5222.
16. S. Kawashima and H. Nakano: IEEE J. Solid-State Circuits 37 (2002) 592.
17. C. L. Sun, S. Y. Chen, C. C. Liao, and A. Chin: Appl. Phys. Lett. 85 (2004) 4726.
18. S.-M. Yoon, E. Tokumitsu, and H. Ishiwara: Jpn. J. Appl. Phys. 39 (2000) 2119.
19. S. Sakai and R. Ilangovan: IEEE Electron Device Lett. 25 (2004) 369.
20. Y. Shimada, Y. Kato, T. Yamada, K. Tanaka, T. Otsuki, Z. Chen, M. Lim, V. Joshi, L. McMillan, and C. A. Paz de Araujo: Integrated Ferroelectr. 40 (2001) 41.
21. Y. Kato, T. Yamada, and Y. Shimada: IEEE Trans. Electron Devices 52 (2005) 2616.