Determining weak Fermi-level pinning in MOS devices by conductance and capacitance analysis and application to GaAs MOS devices

Solid-State Electronics

Volumn 51, Issue 8, 2007, Pages 1101-1108

  Martens, K ^a,b   Wang, W F ^a,b   Dimoulas, A ^c   Borghs, G ^a,b   Meuris, M ^a   Groeseneken, G ^a,b   Maes, H E ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c INSTITUTE OF NANOSCIENCE AND NANOTECHNOLOGY   (Greece)

Author keywords

Capacitance; Conductance; Fermi level pinning; GaAs; Germanium; III V; Interface states; MOS

Indexed keywords

CAPACITANCE; ELECTRIC CONDUCTANCE; EXTRACTION; FERMI LEVEL; SEMICONDUCTING GALLIUM ARSENIDE;

FERMI-LEVEL PINNING; INTERFACE STATES;

MOS DEVICES;

EID: 34547692773     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.06.002     Document Type: Article

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