Design of an interconnect architecture and signaling technology for parallelism in communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 8, 2007, Pages 881-893

  Kim, Jongsun ^a,b,c   Verbauwhede, Ingrid ^a,b,d   Chang, Mau Chung Frank ^a,b  

^a IEEE   (United States)

^b University of California   (United States)

^c Samsung Advanced Institute of Technology (SAIT)   (South Korea)

^d UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Bandwidth; Bus; Input output (I O) interface; Inter chip communication; Interconnect; Latency

Indexed keywords

INPUT/OUTPUT (I/O) INTERFACE; INTER-CHIP COMMUNICATION; INTERCONNECTS; LATENCY;

BANDWIDTH; NETWORK PROTOCOLS; TELECOMMUNICATION LINKS; TIME DIVISION MULTIPLEXING;

INTERCONNECTION NETWORKS;

EID: 34547419025     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.900739     Document Type: Conference Paper

References (29)

1. Int. Technology Roadmap for Semiconductors, "ITRS roadmap," (2005). [Online]. Available: http://www.itrs.net/Common/2005ITRS/ Home2005.htm.
2. S. Fuller, RapidIO: The Embedded System Interconnect. New York: Wiley, 2005.
3. W. Stallings, Computer Organization and Architecture; Designing for Performance. Englewood Cliffs, NJ: Prentice-Hall, 2003.
4. J. Kim, Z. Xu, and M. F. Chang, "A 2-Gbps/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability," in Proc. IEEE Custom Integr. Circuits Conf. (CICC), 2003, pp. 317-320.
5. Z. Xu, H. Shin, J. Kim, M. F. Chang, and C. Chien, "Giga bit/s CDMA interconnect transceiver chip-set with multilevel signal data recovery for re-configurable VLSI system," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2003, pp. 322-323.
6. J. Kim, Z. Xu, and M. F. Chang, "Re-configurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2003, pp. II-33-36.
7. I. Verbauwhede and M.-C. F. Chang, "Reconfigurable interconnect for next generation systems," in Proc. ACM Int. Workshop Syst. Level Interconnect Prediction (SLIP), 2002, pp. 71-74.
8. IBM, Hopewell Junction, NY, "IBM CoreConnect bus architecture," (1999). [Online]. Available: http://www-03.ibm.com/chips/products/coreconnect/
9. B. A. Forouzan, Data Communications and Networking. New York: McGraw-Hill, 2004.
10. K. Lee, S. Lee, and H. Yoo, "Low-power network-on-chip for high-performance SoC design," IEEE Trans. Very Large Scale Integr: Syst., vol. 14, no. 2, pp. 148-160, Feb. 2006.
11. J. L. Hennessy and D. A. Patterson, Computer Architecture; A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 2003.
12. A. A. Jerraya and W. Wolf, Multipmcesor Systems-on-Chips. San Mateo, CA: Morgan Kaufmann, 2005.
13. V. Cuppu and B. Jacob, "Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance," in Proc. 28th Annu. Int. Symp. Comput. Arch., 2001, pp. 62-71.
14. B. Sklar, Digital Communications; Fundamentals and Applications. Englewood Cliffs, NJ: Prentice-Hall, 2001.
15. T. Takahashi, T. Muto, Y. Shirai, F. Shirotori, Y. Takada, A. Yamagiwa, A. Nishida, A. Hotta, and T. Kiyuna, "110-GB simultaneous bidirectional transceiver logic synchronized with a system clock," IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1526-1532, Nov. 1999.
16. J. Zerbe, P. Chau, C. Werner, T. Thrush, H. Liaw, B. Garlepp, and K. Donnelly, "1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 752-760, May 2001.
17. HyperTransport Consortium, "Testing HyperTransport backgrounder," (2001). [Online]. Available: http://www.hypertransport.org/ docs/dg/HT_Backgrounder_final_v8.pdf
18. ARM, "AMBA Specification Rev.2," (1999). [Online], Available: http://www.arm.com/products/solutions/AMBA_Spec.html
19. R. Ho, K. Mai, and M. Horowitz, "Efficient on-chip global interconnects," in Proc. Symp. VLSI Circuits, 2003, pp. 271-274.
20. A. P. Jose, G. Patounakis, and K. L. Shepard, "Near speed-of-light on-chip interconnects using pulsed current-mode signaling," in Proc. Symp. VLSI Circuits, 2005, pp. 108-111.
21. W. Dally et al., "Route packets, not wires: On-chip interconnection networks," in Proc. Design Autom. Conf, 2001, pp. 684-689.
22. D. Wiklund, S. Sathe, and D. Liu, "Benchmarking of on-chip interconnection networks," in Proc. Int. Conf. Microelectron., 2004, pp. 621-624.
23. T. Granberg, Digital Techniques for High-Speed Design. Englewood Cliffs, NJ: Prentice-Hall, 2004.
24. Myricom Corp., Arcadia, CA, "Myricomhomepage," (1994). [Online]. Available: http://www.myricom/
25. Dolphin Corp., Marlborough, MA, "PCI SCI-64 adapter card," (1996). [Online]. Available: http://www.dolphinics.no/dics_pci.sci64.htm
26. A. Bhatt, "Creating a third generation I/O interconnect," (2004). [Online], Available: http://www.intel.com/technology/pciexpress/devnet/ docs/WhatisPCIExpress.pdf
27. HyperTransport Consortium, "HyperTransport consortium," (2006). [Online], Available: http://www.hypertransport.org/tech/index.cfm.
28. RapidIO, "RapidIO technology overview and applications," (2005). [Online]. Available: http://www.rapidio.org/education/documents/ RapidIO_Overview-Apps_v07.pdf
29. InfiniBand, Beaverton, OR, "InfiniBand architecture overview," (2002). [Online]. Available: http://www.infinibandta.org/itinfo/