Benchmarking of on-chip interconnection networks

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2004, Pages 621-624

  Wiklund, Daniel ^a   Sathe, Sumant ^a   Liu, Dake ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Benchmarking; Network on chip; Simulation

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; CONSTRAINT THEORY; MATHEMATICAL MODELS; QUALITY OF SERVICE; ROUTERS; TELECOMMUNICATION TRAFFIC; THROUGHPUT;

BUFFERS; INTERCONNECT ARCHITECTURES; INTERCONNECT DESIGN; NETWORK-ON-CHIP;

NETWORKS (CIRCUITS);

EID: 21644479647     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. K Goossens, J van Meerbergen, A Peeters, and P Wielage, "Networks on silicon: Combining best-effort and guaranteed services," in Proceedings of the design automation and test conference. Mar. 2002.
2. S Sathe, D Wiklund, and D Liu, "Design of a switching node (router) for on-chip networks," in Proc of the ASICON 2003 conference, Oct. 2003.
3. P Guerrier and A Greiner, "A generic architecture for on-chip packet-switched interconnections," in Proc of the design and test in Europe (DATE) conference, 2000.
4. I Saastamoinen, D Sigüenza-Tortosa, and J Nurmi, "Interconnect IP node for future system-on-chip designs," in IEEE int'l workshop on Electronic design. Test, and Applications, 2002.
5. D Wiklund and D Liu, "Socbus: Switched network on chip for hard real time systems," in Proc of the Int'l Parallel and Distributed Processing Symposium (IPDPS), Apr. 2003.
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8. Berkeley Design Technology, Inc. (BDTI), "Evaluating DSP processor performance," http://www.bdti.com.