A 2.7Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Xu, Zhiwei ^a   Shin, Hyunchol ^b   Kim, Jongsun ^a   Chang, M Frank ^a   Chien, Charles ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b QUALCOMM INC   (United States)

^c G Plus Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CODE DIVISION MULTIPLE ACCESS; DEMODULATORS; JITTER; PACKET SWITCHING; TIMING CIRCUITS; TRANSMITTERS; VLSI CIRCUITS;

ASYNCHRONOUS ERROR DETECTION CORRELATOR; CLOCK-DATA RECOVERY CIRCUITS; PSEUDO-NOISE CODES; SMART INTERCONNEST SYSTEMS; WALSH CODES;

TRANSCEIVERS;

EID: 0037631099     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M.F. Chang et al. "RF/Wireless Interconnect for Inter- and Intra-Chip Communications." Proceedings of the IEEE, vol. 89, (no.4), IEEE, April 2001
2. R. Yoshimura et al. "DS-CDMA Wired Bus with Simple Interconnection Topology for Parallel Processing System LSIs," ISSCC Digest of Tech. Papers, pp. 370-371, Feb. 2000.
3. R. Farjad-Rad et al. "A 0.3μm CMOS 8-Gb/s 4-PAM Serial Link Transceiver," Symposium on VLSI Circuits Digest of Technical Papers, May 1999
4. M. Soyuer et al. "A Monolithic 2.3Gb/s 100mW Clock and Data Recovery Circuit," ISSCC Digest of Tech. Papers, pp. 158-159, Feb. 1993.