A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 317-320

  Kim, Jongsun ^a   Xu, Zhiwei ^a   Chang, M Frank ^a  

^a Engineering IV   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; DIRECT SEQUENCE SYSTEMS; MODULATORS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; TRANSCEIVERS;

BACK-SIDE BUS; CHIP-TO-CHIP INTERCONNECT; FRONT-SIDE BUS; MEMORY SUBSYSTEM; MULTI-CHIP ACCESS BUS INTERFACE;

INTERFACES (COMPUTER);

EID: 0242443732     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. M. Frank Chang, Vwani Roychowdhury, Liyang Zhang, Hyunchol Shin, Y. Qian, "RF/Wireless Interconnect for Inter- and Intra-Chip Communications," Proceedings of the IEEE, Vol. 89, Apr. 2001.
2. R. Yoshimura, T. Boon Keat, Toru Ogawa, S. Hatanaka, T. Matsuoka, K. Taniguchi, "DS-CDMA Wired Bus with Simple Interconnection Topology for Parallel Processing System LSIs," ISSCC Digest of Tech. Papers, pp. 370-371, Feb. 2000.
3. Zhiwei Xu, Hyunchol Shin, Jongsun Kim, M. Frank Chang, Charles Chien, "A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems," ISSCC Digest of Tech. Papers, pp. 82-83, Feb. 2003.
4. Jongsun Kim, Zhiwei Xu, M. Frank Chang, "Re-configurable Memory Bus Systems using Multi-Gbps/pin CDMA I/O Transceivers", Proceedings of ISCAS 2003, in press.
5. R. Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee, "A 0.4-um CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter," IEEE J. Solid-State Circuits, pp.580-585, May 1999.
6. Jared L. Zerbe, P. S. Chau, C. W. Werner, T. P. Thrush, et al., "1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus," Symposium on VLSI circuits, pp.128-131, Jun. 2000.
7. Haw-Jyh Liaw, G.-J. Yeh, Pak S. Chau, G. Pitner, "A 1.6 Gbit/s/pin Multilevel Parallel Interconnection," DesignCon 2001, Jan. 2001.
8. Vinodh Cuppu, Bruce Jacob, "Concurrency, Latency, or System Overhead: Which has the largest impact on uniprocessor DRAM-system performance," Computer Architecture, 28th Annual International Symposium on, pp. 62-71, 2001.