A 372ps 64-bit adder using fast pull-up logic in 0.18-μm CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 13-16

  Kim, Jooyoung ^a   Lee, Kangmin ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC LOAD MANAGEMENT; LOGIC CIRCUITS; STATIC ANALYSIS; TREES (MATHEMATICS);

DOMINO-STATIC ADDERS; FAST PULL-UP LOGIC (FPL); LOAD DISTRIBUTION METHOD;

ADDERS;

EID: 34547347615     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. T self-timed CMOS logic for low subthreshold current multigigabit synchronous DRAM," IEEE Transaction on Circuits and Systems II, Volume 45, pp. 1263-1271, Sept. 1998
2. S.-J. Lee and H.-J. Yoo, "Race logic architecture (RALA): a novel logic concept using the race scheme of input variables," IEEE JSSC, Vol.37, pp.191-201, Feb. 2002
3. S.-J. Lee, R. Woo and H.-J.Yoo, "480 ps 64-bit race logic adder," Digest of Tech. Papers Symposium on VLSI Circuits 2001. pp.27-28
4. R. Woo, S.-J. Lee and H.-J. Yoo, "670ps, 64bit Dynamic Low-power Adder Design," Proceedings of ISCAS, Vol. 1, pp.28-31, May 2000
5. Mathew, S. Anders, M. Krishnamurthy, R.K. and Borkar, S, "A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core,"JSSC, Volume 38, pp.689 - 695, May 2003
6. Yuke Wang, C. Pai, and Xiaoyu Song, "The Design of Hybrid Carry-Lookahead/Carry-Select Adders," IEEE Transactions on Circuits and Systems II, Volume 49, pp. 16-24, Jan.2002
7. R. Zlatanovici, B. Nikolic, "Power-performance optimal 64-bit carry-lookahead adders," ESSCIRC 2003, pp.321 - 324
8. Mathew, S. et al., "A 4-GHz 300-mW 64-bit Integer Excution ALU With Dual Supply Voltages in 90-nm CMOS," IEEE JSSC, Volume 40, pp.44-51, Jan. 2005
9. Sheng Sun, et al., "409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS" Proceedings of IEEE Computer Society Annual Symposium on VLSI pp.52 - 58, May 2005.
10. A. Neve, H.Schettler, T.Lugwig, D.Flandre, "Power-delay product minimization in high-performance 64-bit carry-select adders," Trans. VLSI, March 2004, pp.235 - 244.
11. D. Stasiak, F. Mounes-Toussi, S.N.Storino, "A 440-ps 64-bit adder in 1.5-V 0.18um partially depleted SOI technology,"JSSC, Oct.2001.
12. J.Park, H.Ngo, J.Silberman, S.Dhong, "470-ps 64-bit parallel binary adder," Digest of Symposium on VLSI Cir., pp. 192-193, June 2000