Dual-VT self-timed CMOS logic for low subthreshold current multigigabit synchronous DRAM

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 9, 1998, Pages 1263-1271

  Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Cmos memory integrated circuits; Low voltage; Subthreshold leakage

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; COMPUTER SOFTWARE; DELAY CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; OPTIMIZATION;

SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0032167226     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.718594     Document Type: Article

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