A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 10, 2001, Pages 1546-1552

  Stasiak, D L ^a   Mounes Toussi, F ^a   Storino, S N ^a  

^a IBM   (United States)

Author keywords

Adders; Digital circuits; Silicon on insulator technology

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

DYNAMIC CIRCUITS; FLOATING BODY EFFECTS;

ADDERS;

EID: 0035473304     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.953483     Document Type: Article

References (9)

1. TM microprocessor with copper interconnects
2. TM microprocessor with copper interconnects
3. Partially depleted SOI technology for digital logic