The design of hybrid carry-lookahead/carry-select adders

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 49, Issue 1, 2002, Pages 16-24

  Wang, Yuke ^b   Pai, C ^c   Song, Xiaoyu ^a,d  

^a IEEE   (United States)

^b The University of Texas at Dallas   (United States)

^c Gina Cody School of Engineering and Computer Science   (Canada)

^d Portland State University   (United States)

Author keywords

Adders; High speed circuits; VLSI

Indexed keywords

CARRY-LOOKAHEAD ADDERS (CLA);

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC SIGNAL SYSTEMS; VLSI CIRCUITS;

ADDERS;

EID: 0036098656     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.996053     Document Type: Article

References (10)

1. A spanning tree carry lookahead adder
2. A recursive carry-lookahead/carry-select hybrid adder
3. High speed addition in CMOS
4. A 3.1 ns 32B CMOS adder in multiple output domino logic
5. A 4.5 ns 96B CMOS adder design
6. High speed binary adder
7. Some optimal schemes for ALU implementation in VLSI technology
8. Variants of an improved carry look ahead adder
9. A regular layout for parallel adders