670 ps, 64 bit dynamic low-power adder design

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages

  Woo, Ramchan ^a   Lee, Se Joong ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT;

DYNAMIC LOW-POWER ADDERS; PARALLEL QUATERNARY-TREE;

ADDERS;

EID: 0033715995     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857017     Document Type: Conference Paper

References (7)