Reliability of ultra thin gate oxide CMOS devices: Design perspective

2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Volumn , Issue , 2006, Pages

  Parthasarathy, C R ^a,c   Denais, M ^a   Huard, V ^b   Ribes, G ^a   Vincent, E ^a   Bravaix, A ^c  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

^c AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; GATE DIELECTRICS; GATES (TRANSISTOR); HOT CARRIERS;

OXIDE BREAKDOWN; ULTRA THIN GATE OXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 42749102873     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2006.220808     Document Type: Conference Paper

References (25)

1. ITRS Roadmap 2005 Edition: Process Integration, Devices and Structures.
2. st 2003.
3. M. Denais et al "On-the-fly characterization of NBTI in ultrathin gate-oxide PMOSFET's", International Electron Device Meeting Technical Digest, pp. 109-112, 2004.
4. S. Rangan et al "Universal recovery behavior of negative bias temperature instability", International Electron Device Meeting Technical Digest, pp. 341-344, 2003.
5. C Schlunder et al, "On the Degradation of P-MOSFETs in Analog and RF Circuits under Inhomogenous Negative Bias Temperature Stress", International Reliability Physics Symposium Proceedings, pp. 5-10, 2003.
6. BS Doyle et al "NBTI-Enhanced Hot Carrier Damage in pChannel MOSFET's", International Electron Device Meeting Technical Digest, pp. 529-533, 1991.
7. G. La Rosa et al "NBTT-Channel Hot Carrier Effects in PMOSFETS in Advanced CMOS Technologies", International Reliability Physics Symposium Proceedings, pp. 282-286, 1997.
8. H Aono et al "NBT-induced Hot Carrier (HC) Effect: Positive Feedback Mechanism in p-MOSFET's Degradation", Proceedings of International Reliability Physics Symposium Proceedings, pp. 79-85, 2002.
9. CR Parthasarathy et al, "Characterization and Modeling NBTT for Design-in Reliability", Tutorial Paper, IEEE International Integrated Reliability Workshop Final Report, pp. 158-162, October 2005.
10. V. Huard, M. Denais, "Hole trapping effect on methodology for DC and AC Negative Bias Temperature Instability Measurements in PMOS transistors", Proceedings of International Reliability Physics Symposium Proceedings, pp. 40-45, 2004.
11. A. Bravaix, D. Goguenheim, V. Huard, M. Denais, C. Parthasarathy, F. Perrier, N. Revil, E. Vincent, "Impacts of the Recovery Phenomena on the Worst-Case of Damage in DC/AC stressed Ultra-thin NO gate-Oxide MOSFETs", Microelectronics Reliab., Vol. 45, pp. 1370-1375, 2005.
12. M.Denais et al, "Paradigm Shift for NBTI Characterization in Ultra-scaled CMOS Technologies", to be presented at IRPS 2006.
13. G Chen et aTDynamic NBTI of p-MOS Transistors and Its Impact on MOSFET Scaling", IEEE Electron Device Letters, Vol.23, No. 12, pp. 734-736, December 2002.
14. CR Parthasarathy et al, "New Insights into Recovery Characteristics post NBTI Stress" to be presented at IRPS 2006
15. R Woltjer et al, "Three Hot-Carrier Degradation Mechanisms in Deep-Submicron PMOSFET's" IEEE Transactions on Electron Devices, Vol.42, No. 1, pp. 109-115, January 1995.
16. C Hu et al, " Hot-Electron-Induced MOSFET Degradation -Model, Monitor, and Improvement", IEEE Transactions on Electron Devices, Vol ED-32, No.2, pp375-385, February 1985.
17. KR Mistry et al, "AC Hot Carrier Lifetimes in Oxide and ROXNOX N-Channel MOSFET's" International Electron Device Meeting Technical Digest, pp. 727-730, 1991.
18. KN Quader et al, "Hot-Carrier-Reliability Design Rules for Translating Device Degradation to CMOS Digital Circuit Degradation", IEEE Transactions on Electron Devices, Vol.41, No.5, pp. 681-690, May 1994.
19. MG Ancona et al, "Lateral Distribution of Hot-electron Induced Interface Traps in MOSFETs", IEEE Transactions on Electron Devices, Vol.35 No.12, pp. 2221-2228, December 1988.
20. W Weber et al, "Dynamic Degradation in MOSFET's - Part II: Application in the Circuit Environment", IEEE Transactions on Electron Devices, Vol.38 No.8, pp. 1859-1867, August 1991.
21. C Hu, "AC Effects in IC Reliability", Microelectronics Reliability, Vol.36, No. 11/12, pp. 1611-1617, 1996.
22. F Monsieur et al, "A Thorough Investigation of Progressive Breakdown in Ultra-thin Oxides, Physical Understanding and Application for Industrial Reliability Assessment", International Reliability Physics Symposium Proceedings, pp. 45-54, 2002.
23. V Huard et al "Impact of Progressive Breakdown on Digital Circuits", Internal Report.
24. Rodriguez R et al, "The Impact of Gate-Oxide Breakdown on SRAM Stability", IEEE Electron Device Letters, Vol 23, No 9, pp. 426-429, September 2004
25. Mueller K et al, "6-T Cell Circuit dependent GOX SED Model for accurate prediction of observed VCCMIN Test Voltage Dependency", International Reliability Physics Symposium Proceedings, pp. 426-429, 2004.