New hole trapping characterization during NBTI in 65NM node technology with distinct nitridation processing

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2004, Pages 121-124

  Denais, M ^a,d   Bravaix, A ^d   Huard, V ^b   Parthasarathy, C ^a,d   Bidaud, M ^b   Ribes, G ^a   Barge, D ^b   Vishnubhotla, L ^c   Tavel, B ^b   Rey Tauriac, Y ^a   Perrier, F ^b   Revil, N ^a   Arnaud, F ^a   Stolk, P ^b  

^a STMICROELECTRONICS   (France)

^b CRandD labs   (France)

^c Freescale Semiconductors   (France)

^d AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGRADATION; GATES (TRANSISTOR); INTERFACES (MATERIALS); ION IMPLANTATION; LEAKAGE CURRENTS; LOGIC DEVICES; OXIDATION; POLYSILICON; THRESHOLD VOLTAGE; TRANSISTORS;

GATE OXIDES; HOLE TRAPPING CHARACTERIZATION; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); NITRIDATION PROCESSING;

HOLE TRAPS;

EID: 21644479596     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. "Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors", M. Ershov, S. Saxena, H. Karbasi, S. Winters, S. Minehane, J. Babcock, R. Lindley, P. Clifton, M. Redford, and A. Shibkov, Applied Physics Letters Vol 83(8), p. 1647, August 25, 2003.
2. "Hole trapping effect on methodology for DC and AC Negative Bias Temperature Instability Measurements in PMOS transistors", V. Huard, M. Denais, IEEE International Reliability Physics Symposium Proceedings, p. 40, 2004.
3. "Universal Recovery Behavior of Negative Bias Temperature Instability", S. Rangan, N. Mielke, E.C.C. Yeh, IEEE International Electron Devices Meeting, p. 341, 2003.
4. "Decoupled Plasma Nitridation for Ultra-thin Gate Oxides for 60-90nm Technologies", M.Bidaud, J-P.Carrère. F.Boeuf, C.Dachs, C.Parthasarathy, F.Guyader, Electro-Chemical Society Spring Meeting, 2003.
5. "The Main Challenges in the characterization of ultra-thin gate oxides in deep sub-micron CMOS Technologies", D.Roy, International Conference on Defects - Recognition, Imaging and Physics in Semiconductors (DRIP X), Invited paper, 2003.
6. "Charge Transfer by Direct Tunneling in Thin-Oxide Memory Transistor" A.V Ferris-Prabhu, IEEE Transactions on Electron Devices, Vol. ED-24, NO. 5, 1977.
7. "Oxide field dependence of interface trap generation during Negative Bias Temperature Instability in PMOS", M.Denais, V.Huard, C.Parthasarathy, G.Ribes, F.Perrier, N.Revil, A.Bravaix, IEEE Integrated Reliability Workshop proceedings, 2004.