A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 246-251

  Alam, S M ^a   Troxel, D E ^a   Thompson, C V ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Availability; Circuit analysis; Circuit simulation; Computational modeling; Design methodology; Integrated circuit technology; Performance analysis; Polymers; Three dimensional integrated circuits; Wafer bonding

Indexed keywords

AVAILABILITY; CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; POLYMERS; THREE DIMENSIONAL INTEGRATED CIRCUITS; WAFER BONDING;

COMPUTATIONAL MODEL; COMPUTER AIDED DESIGN TOOLS; DESIGN METHODOLOGY; ENCRYPTION PROCESSORS; ESSENTIAL ELEMENTS; INTEGRATED CIRCUIT TECHNOLOGY; PERFORMANCE ANALYSIS; PERFORMANCE COMPARISON;

ELECTRIC NETWORK ANALYSIS;

EID: 84948451001     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996742     Document Type: Conference Paper

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