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Volumn 51, Issue 6, 2007, Pages 936-940

Characterization of double gate TFTs fabricated in advanced SLS ELA polycrystalline silicon films

Author keywords

Double gate MOS; Lateral solidification; Polysilicon; Thin film transistors

Indexed keywords

AVALANCHE EFFECT; DOUBLE GATE MOS; LATERAL SOLIDIFICATION; THRESHOLD CONTROL;

EID: 34250829701     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.04.003     Document Type: Article
Times cited : (12)

References (15)
  • 1
    • 84888744985 scopus 로고    scopus 로고
    • Matsuo T, Muramatsu T. CG silicon technology and development of system on panel. In: Proceedings of the SID international symposium, 2004. p. 856.
  • 3
    • 0035474080 scopus 로고    scopus 로고
    • Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress
    • Chang K.M., Chung Y.H., Lin G.M., Deng C.G., and Lin J.H. Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress. IEEE Electron Dev Lett EDL-22 (2001) 475-477
    • (2001) IEEE Electron Dev Lett , vol.EDL-22 , pp. 475-477
    • Chang, K.M.1    Chung, Y.H.2    Lin, G.M.3    Deng, C.G.4    Lin, J.H.5
  • 4
    • 0035249625 scopus 로고    scopus 로고
    • Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors
    • Farmakis F.V., Brini J., Kamarinos G., and Dimitriadis C.A. Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors. IEEE Electron Dev Lett EDL-22 (2001) 74-76
    • (2001) IEEE Electron Dev Lett , vol.EDL-22 , pp. 74-76
    • Farmakis, F.V.1    Brini, J.2    Kamarinos, G.3    Dimitriadis, C.A.4
  • 5
    • 0036611165 scopus 로고    scopus 로고
    • A poly-Si TFT fabricated by excimer laser recrystallization on floating active structure
    • Kim C.-H., Song I.-H., Nam W.-J., and Han M.-K. A poly-Si TFT fabricated by excimer laser recrystallization on floating active structure. IEEE Electron Dev Lett EDL-23 (2002) 315-317
    • (2002) IEEE Electron Dev Lett , vol.EDL-23 , pp. 315-317
    • Kim, C.-H.1    Song, I.-H.2    Nam, W.-J.3    Han, M.-K.4
  • 6
    • 0042164526 scopus 로고    scopus 로고
    • Assessment of the performance of laser-based lateral crystallization technology via analysis and modeling of polysilicon thin-film-transistor mobility
    • Voutsas A.T. Assessment of the performance of laser-based lateral crystallization technology via analysis and modeling of polysilicon thin-film-transistor mobility. IEEE Trans Electron Dev ED-50 6 (2003) 1494-1500
    • (2003) IEEE Trans Electron Dev , vol.ED-50 , Issue.6 , pp. 1494-1500
    • Voutsas, A.T.1
  • 7
    • 0000897114 scopus 로고    scopus 로고
    • Sequential lateral solidification of thin silicon films on SiO2
    • Sposili R.S., and Im J.S. Sequential lateral solidification of thin silicon films on SiO2. Appl Phys Lett 69 19 (1996) 2864-2866
    • (1996) Appl Phys Lett , vol.69 , Issue.19 , pp. 2864-2866
    • Sposili, R.S.1    Im, J.S.2
  • 8
    • 0037416534 scopus 로고    scopus 로고
    • Parametric investigation of SLS-processed poly-silicon thin films for TFT applications
    • Crowder M.A., Moriguchi M., Mitani Y., and Voutsas A.T. Parametric investigation of SLS-processed poly-silicon thin films for TFT applications. Thin Solid Films 427 (2003) 101-107
    • (2003) Thin Solid Films , vol.427 , pp. 101-107
    • Crowder, M.A.1    Moriguchi, M.2    Mitani, Y.3    Voutsas, A.T.4
  • 9
    • 0348195954 scopus 로고    scopus 로고
    • Effect of process parameters on the structural characteristics of laterally-grown polycrystalline silicon films
    • Voutsas A.T., Limanov A., and Im J.S. Effect of process parameters on the structural characteristics of laterally-grown polycrystalline silicon films. J Appl Phys 94 12 (2003) 7445-7452
    • (2003) J Appl Phys , vol.94 , Issue.12 , pp. 7445-7452
    • Voutsas, A.T.1    Limanov, A.2    Im, J.S.3
  • 10
    • 33644593302 scopus 로고    scopus 로고
    • Hatano M, Sato T, Matsumura M, Toyota Y, Tai M, Ohkura M, et al. System on display with LTPS-TFTs formed using SELAX technology. In: Proceedings of the 12th international display workshop/Asia display (IDW/AD '05), 2005. p. 953-6.
  • 11
    • 15544371310 scopus 로고    scopus 로고
    • Effect of silicon thickness on the degradation mechanisms of sequential-laterally-solidified polycrystalline silicon thin-film-transistors during hot-carrier stress
    • Voutsas A.T., Kouvatsos D.N., Michalas L., and Papaioannou G.J. Effect of silicon thickness on the degradation mechanisms of sequential-laterally-solidified polycrystalline silicon thin-film-transistors during hot-carrier stress. IEEE Electron Dev Lett EDL-26 3 (2005) 181-184
    • (2005) IEEE Electron Dev Lett , vol.EDL-26 , Issue.3 , pp. 181-184
    • Voutsas, A.T.1    Kouvatsos, D.N.2    Michalas, L.3    Papaioannou, G.J.4
  • 12
    • 4544343899 scopus 로고    scopus 로고
    • Effects of hot carrier and irradiation stresses on advanced excimer laser annealed polycrystalline silicon thin film transistors
    • Kouvatsos D.N., Davidovic V., Papaioannou G.J., Stojadinovic N., Michalas L., Exarchos M., et al. Effects of hot carrier and irradiation stresses on advanced excimer laser annealed polycrystalline silicon thin film transistors. Microelectron Reliab 44 (2004) 1631-1636
    • (2004) Microelectron Reliab , vol.44 , pp. 1631-1636
    • Kouvatsos, D.N.1    Davidovic, V.2    Papaioannou, G.J.3    Stojadinovic, N.4    Michalas, L.5    Exarchos, M.6
  • 13
    • 33751440305 scopus 로고    scopus 로고
    • Kouvatsos DN, Papaioannou GJ, Exarchos M, Michalas L, Voutsas AT. Effect of hot carrier stress on the performance, trap densities and transient behavior of SLS ELA TFTs. In: Proceedings of the ESSDERC, 2005. p. 395.
  • 14
    • 0025519501 scopus 로고
    • Analytical models of subthreshold swing and threshold voltage fot thin- and ultra-thin-film SOI MOSFETs
    • Balestra F., Benachir M., Brini J., and Ghibaudo G. Analytical models of subthreshold swing and threshold voltage fot thin- and ultra-thin-film SOI MOSFETs. IEEE Trans Electron Dev ED-37 11 (1990) 2303-2311
    • (1990) IEEE Trans Electron Dev , vol.ED-37 , Issue.11 , pp. 2303-2311
    • Balestra, F.1    Benachir, M.2    Brini, J.3    Ghibaudo, G.4
  • 15
    • 3142695076 scopus 로고    scopus 로고
    • Double gate (DG)-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm low-voltage/low-power circuit design
    • Mitra S., Salman A., Ioannou D.P., Tretz C., and Ioannou D.E. Double gate (DG)-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm low-voltage/low-power circuit design. Solid-State Electron 48 10-11 (2004) 1727-1732
    • (2004) Solid-State Electron , vol.48 , Issue.10-11 , pp. 1727-1732
    • Mitra, S.1    Salman, A.2    Ioannou, D.P.3    Tretz, C.4    Ioannou, D.E.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.