Double gate (DG)-SOI ratioed logic with symmetric DG load - A novel approach for sub 50 nm low-voltage/low-power circuit design

Solid-State Electronics

Volumn 48, Issue 10-11 SPEC. ISS., 2004, Pages 1727-1732

  Mitra, S ^a,d   Salman, A ^b   Ioannou, D P ^a   Tretz, C ^c   Ioannou, D E ^a  

^a Krasnow Institute for Advanced Study   (United States)

^b San Jose Design Center ^*  (United States)

^c IBM   (United States)

^d IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC LOADS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); POLYSILICON; PROCESS CONTROL;

DEPLETION MODES; LOW POWER CIRCUITS; SCALING LIMITS;

MOSFET DEVICES;

EID: 3142695076     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.05.006     Document Type: Conference Paper

References (7)

1. International SEMATECH, International Technology Roadmap for Semiconductors (ITRS) 2002.
2. Solomon P.M., Guarini K.W., Zhang Y., Chan K., Jones E.C., Cohen G.M., et al. Two gates are better than one [double-gate MOSFET process]. IEEE Circ. Dev. Magazine. 19(1):2003;48.
3. t asymmetric-gate FinFET devices. IEEE International Electron Devices (IEDM) Tech Digest 2001; 19.5.1.
4. Kim K., Fossum J.G. Double-gate CMOS: symmetrical- versus asymmetrical-gate devices. IEEE Trans. Electron. Dev. 48(2):2001;294.
5. Silvaco Corp., Santa Clara, CA.
6. Zhang R., Roy K. Low-power high-performance double-gate fully depleted SOI circuit design. IEEE Trans. Electron. Dev. 49(5):2002;852.
7. Mitra S, Salman A, Ioannou DP, Ioannou DE. LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load. IEEE International SOI Conference: 2002. p. 66.