Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress

IEEE Electron Device Letters

Volumn 22, Issue 10, 2001, Pages 475-477

  Kow Ming Chang, ^a   Yuan Hung Chung, ^a   Gin Ming Lin, ^a   Chi Gun Deng, ^a   Jian Hong Lin, ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Channel shortening effect; Intra grain bulk states; Polysilicon thin film transistors (poly Si TFTs); Tail states; Transconductance (Gm max)

Indexed keywords

GRAIN BOUNDARIES; LIQUID CRYSTAL DISPLAYS; POLYCRYSTALS; POLYSILICON; STATIC RANDOM ACCESS STORAGE; TRANSCONDUCTANCE;

POLYSILICON THIN-FILM TRANSISTORS;

THIN FILM TRANSISTORS;

EID: 0035474080     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.954916     Document Type: Article

References (9)

1. Physical models for degradation effects in polysilicon thin-film transistors
2. Interface state generation during electric stress in n-channel undoped hydrogenated polysilicon thin-film transistors
3. Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors
4. Reliability evaluation method of low temperature poly-silicon TFT's using dynamic stress
5. Electrical stress in N-and P-channel undoped-hydrogenated polysilicon thin film transistors (TFF's)
6. Degradation of polysilicon TFT's during dynamic stress
7. Differentiation of effects due to grain boundary traps in laser annealed poly-Si thin film transistors
8. Grain and grain-boundary control of the transfer characteristics of large-grain polycrystalline silicon thin-film transistors
9. Modelling of laser-annealed polysilicon TFT characteristics