Efficient gate delay modeling for large interconnect loads

Proceedings of the IEEE Multi-Chip Module Conference

Volumn , Issue , 1996, Pages 202-207

  Kahng, Andrew B ^a   Muddu, Sudhakar ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ITERATIVE METHODS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; TRANSFER FUNCTIONS; TREES (MATHEMATICS);

DRIVING POINT ADMITTANCE; GATE DELAY; HIGH LEVEL SYNTHESIS; INTERCONNECT MODELLING; LOAD INTERCONNECT TREE; REDUCED ORDER MODELS;

MULTICHIP MODULES;

EID: 0029776259     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)