A floating-gate programmable array of silicon neurons for central pattern generating networks

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3157-3160

  Tenore, Francesco ^a   Jacob Vogelstein, R ^b   Etienne Cumrnings, Ralph ^a   Cauwenherghs, Gert ^c   Hasler, Paul ^d  

^a Johns Hopkins University   (United States)

^b Johns Hopkins University   (United States)

^c UNIVERSITY OF CALIFORNIA SAN DIEGO   (United States)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PATTERN GENERATOR CHIP; REPROGRAMMABLE CONNECTIVITY;

MICROPROCESSOR CHIPS; NEURONS; PHASE LOCKED LOOPS; SENSORY FEEDBACK; SILICON;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34248657766     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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