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Volumn 50, Issue 10, 2003, Pages 2144-2153

A physical compact model of DG MOSFET for mixed-signal circuit applications - Part II: Parameter extraction

Author keywords

Compact model; Double gate (DG) MOSFET; Mixed signal; Parameter extraction

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; EXTRAPOLATION; PARAMETER ESTIMATION; SEMICONDUCTOR DEVICE MODELS; SIGNAL PROCESSING; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

EID: 0141974954     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.817480     Document Type: Article
Times cited : (8)

References (17)
  • 2
    • 0024105667 scopus 로고
    • A physically based mobility model for numerical simulation of nonplanar devices
    • Nov.
    • C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Computer-Aided Design, vol. 7, pp. 1164-1170, Nov. 1988.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , pp. 1164-1170
    • Lombardi, C.1    Manzini, S.2    Saporito, A.3    Vanzi, M.4
  • 3
    • 0028747841 scopus 로고
    • On the universality of inversion layer mobility in Si MOSFET's: Part I-Effects of substrate impurity concentration
    • Dec.
    • S. Takagi, S. A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part I-Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, Dec. 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , pp. 2357-2362
    • Takagi, S.1    Toriumi, S.A.2    Iwase, M.3    Tango, H.4
  • 4
    • 0018960654 scopus 로고
    • Velocity of surface carriers in inversion layer on silicon
    • R. W. Coen and R. S. Muller, "Velocity of surface carriers in inversion layer on silicon," Solid State Electron., vol. 23, no. 1, pp. 35-40, 1980.
    • (1980) Solid State Electron. , vol.23 , Issue.1 , pp. 35-40
    • Coen, R.W.1    Muller, R.S.2
  • 7
    • 0026116330 scopus 로고
    • New short-channel n-MOSFET current-voltage model in strong inversion and unified parameter extraction method
    • Mar.
    • B.-J. Moon, C.-K. Park, K. Lee, and M. Shur, "New short-channel n-MOSFET current-voltage model in strong inversion and unified parameter extraction method," IEEE Trans. Electron Devices, vol. 38, pp. 592-602, Mar. 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 592-602
    • Moon, B.-J.1    Park, C.-K.2    Lee, K.3    Shur, M.4
  • 10
    • 0035250378 scopus 로고    scopus 로고
    • Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
    • Feb.
    • K. Kim and J. G. Fossum, "Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , pp. 294-299
    • Kim, K.1    Fossum, J.G.2
  • 12
    • 0036494619 scopus 로고    scopus 로고
    • Advanced model and analysis of series resistance for CMOS scaling into nanometer regime-Part I: Theoretical derivation
    • Mar.
    • S.-D. Kim, C.-M. Park, and J. C. S. Woo, "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime-Part I: Theoretical derivation," IEEE Trans. Electron Devices, vol. 49, pp. 457-466, Mar. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , pp. 457-466
    • Kim, S.-D.1    Park, C.-M.2    Woo, J.C.S.3
  • 13
    • 0036494258 scopus 로고    scopus 로고
    • Advanced model and analysis of series resistance for CMOS scaling into nanometer regime-Part II: Quantitative analysis
    • Mar.
    • ____, "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime-Part II: Quantitative analysis," IEEE Trans. Electron Devices, vol. 49, pp. 467-472, Mar. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , pp. 467-472
    • Kim, S.-D.1
  • 16
    • 0026835430 scopus 로고
    • A novel method to characterize MOS transistors with mixed gate dielectric technologies
    • Mar.
    • R. R. Siergiej and M. H. White, "A novel method to characterize MOS transistors with mixed gate dielectric technologies," IEEE Trans. Electron Devices, vol. 39, pp. 734-737, Mar. 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 734-737
    • Siergiej, R.R.1    White, M.H.2
  • 17
    • 0026817489 scopus 로고
    • Fast simulated diffusion: An optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction
    • Feb.
    • T. Sakurai, B. Lin, and R. Newton, "Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction," IEEE Trans. Computer-Aided Design, vol. 11, pp. 228-234, Feb. 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.11 , pp. 228-234
    • Sakurai, T.1    Lin, B.2    Newton, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.