-
1
-
-
0015604443
-
Design of totally self-checking check circuits for m-out-of-n codes
-
March
-
D. A. Anderson and G. Metze. Design of totally self-checking check circuits for m-out-of-n codes. IEEE Trans. On Computers, C22(3):263-269, March 1973.
-
(1973)
IEEE Trans. on Computers
, vol.C22
, Issue.3
, pp. 263-269
-
-
Anderson, D.A.1
Metze, G.2
-
2
-
-
84937078021
-
Signed-digit number representations for fast parallel arithmetic
-
September
-
A. Avizienis. Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electronic Computers, 10(9):389-400, September 1961.
-
(1961)
IRE Trans. Electronic Computers
, vol.10
, Issue.9
, pp. 389-400
-
-
Avizienis, A.1
-
3
-
-
0021386711
-
Design of totally self-checking checker for 1-out-of-3 code
-
March
-
P. Golan. Design of totally self-checking checker for 1-out-of-3 code. IEEE Trans. on Computers, C33(3):285, March 1984.
-
(1984)
IEEE Trans. on Computers
, vol.C33
, Issue.3
, pp. 285
-
-
Golan, P.1
-
7
-
-
0025403178
-
On the design of combinational totally self-checking 1-out-of-3 code checkers
-
March
-
J.-C. Lo and S. Thanawastien. On the design of combinational totally self-checking 1-out-of-3 code checkers. IEEE Trans. on Computers, 39(3):387-393, March 1990.
-
(1990)
IEEE Trans. on Computers
, vol.39
, Issue.3
, pp. 387-393
-
-
Lo, J.-C.1
Thanawastien, S.2
-
9
-
-
0025210204
-
Generalized signed-digit number systems: A unifying framework for redundant number representations
-
B. Parhami. Generalized signed-digit number systems: A unifying framework for redundant number representations. IEEE Trans. on Computers, 39.
-
IEEE Trans. on Computers
, vol.39
-
-
Parhami, B.1
-
10
-
-
0025401579
-
An efficient TSC 1-out-of-3 code checker
-
March
-
A. M. Paschalis, C. Efstathiou, and C. Halatsis. An efficient TSC 1-out-of-3 code checker. IEEE Trans. on Computers, 39(3):407-411, March 1990.
-
(1990)
IEEE Trans. on Computers
, vol.39
, Issue.3
, pp. 407-411
-
-
Paschalis, A.M.1
Efstathiou, C.2
Halatsis, C.3
-
11
-
-
0030107735
-
Self-checking design in eastern Europe
-
Spring
-
S. J. Piestrak. Self-checking design in eastern Europe. IEEE Design & Test of Computers, 13:16-25, Spring 1996.
-
(1996)
IEEE Design & Test of Computers
, vol.13
, pp. 16-25
-
-
Piestrak, S.J.1
-
12
-
-
0023455521
-
On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic
-
November
-
N. Takagi and S. Yajima. On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic. IEEE Trans. on Computers, C36(11):1310-1317, November 1987.
-
(1987)
IEEE Trans. on Computers
, vol.C36
, Issue.11
, pp. 1310-1317
-
-
Takagi, N.1
Yajima, S.2
-
13
-
-
0142253958
-
On-line error detection in a carry-free adder
-
June 4-7, Unpublished workshop proceedings available at
-
W. J. Townsend, M. A. Thornton, and P. K. Lala. On-line error detection in a carry-free adder. In 11th IEEE/ACM International Workshop on Logic & Synthesis, pages 251-254, June 4-7, 2002. Unpublished workshop proceedings available at http://www.cerc.utexas.edu/~whitney/pubs.html.
-
(2002)
11th IEEE/ACM International Workshop on Logic & Synthesis
, pp. 251-254
-
-
Townsend, W.J.1
Thornton, M.A.2
Lala, P.K.3
-
14
-
-
0028518421
-
Partially strongly fault secure and partially strongly code disjoint 1-out-of-3 code checker
-
October
-
J. Q. Wang and P. K. Lala. Partially strongly fault secure and partially strongly code disjoint 1-out-of-3 code checker. IEEE Trans. on Computers, C43(10):1238-1240, October 1994.
-
(1994)
IEEE Trans. on Computers
, vol.C43
, Issue.10
, pp. 1238-1240
-
-
Wang, J.Q.1
Lala, P.K.2
|