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Volumn , Issue , 2003, Pages 17-22

On-line error detecting constant delay adder

Author keywords

Added delay; Adders; Arithmetic; Circuit testing; Computer errors; Decoding; Encoding; Fault tolerance; Jacobian matrices; Redundancy

Indexed keywords

ADDERS; COMPUTER TESTING; DECODING; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); ERROR DETECTION; ERRORS; JACOBIAN MATRICES; REDUNDANCY;

EID: 36349029047     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214361     Document Type: Conference Paper
Times cited : (7)

References (14)
  • 1
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  • 2
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  • 7
    • 0025403178 scopus 로고
    • On the design of combinational totally self-checking 1-out-of-3 code checkers
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    • J.-C. Lo and S. Thanawastien. On the design of combinational totally self-checking 1-out-of-3 code checkers. IEEE Trans. on Computers, 39(3):387-393, March 1990.
    • (1990) IEEE Trans. on Computers , vol.39 , Issue.3 , pp. 387-393
    • Lo, J.-C.1    Thanawastien, S.2
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    • 0025210204 scopus 로고    scopus 로고
    • Generalized signed-digit number systems: A unifying framework for redundant number representations
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    • IEEE Trans. on Computers , vol.39
    • Parhami, B.1
  • 11
    • 0030107735 scopus 로고    scopus 로고
    • Self-checking design in eastern Europe
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    • S. J. Piestrak. Self-checking design in eastern Europe. IEEE Design & Test of Computers, 13:16-25, Spring 1996.
    • (1996) IEEE Design & Test of Computers , vol.13 , pp. 16-25
    • Piestrak, S.J.1
  • 12
    • 0023455521 scopus 로고
    • On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic
    • November
    • N. Takagi and S. Yajima. On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic. IEEE Trans. on Computers, C36(11):1310-1317, November 1987.
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  • 13
    • 0142253958 scopus 로고    scopus 로고
    • On-line error detection in a carry-free adder
    • June 4-7, Unpublished workshop proceedings available at
    • W. J. Townsend, M. A. Thornton, and P. K. Lala. On-line error detection in a carry-free adder. In 11th IEEE/ACM International Workshop on Logic & Synthesis, pages 251-254, June 4-7, 2002. Unpublished workshop proceedings available at http://www.cerc.utexas.edu/~whitney/pubs.html.
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    • J. Q. Wang and P. K. Lala. Partially strongly fault secure and partially strongly code disjoint 1-out-of-3 code checker. IEEE Trans. on Computers, C43(10):1238-1240, October 1994.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.