An intrinsically robust technique for fault tolerance under multiple upsets

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 180-

  Lisboa C A L ^a   Cairo, L ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC OPERATORS; ELECTROMAGNETIC NOISE; STOCHASTIC ADDERS; TRIPLE MODULAR REDUNDANCY (TMR);

COMPUTER SIMULATION; DIGITAL ARITHMETIC; ELECTROMAGNETISM; ERROR ANALYSIS; FLIP FLOP CIRCUITS; LOGIC GATES; PROBABILITY; RANDOM PROCESSES; REDUNDANCY; SPURIOUS SIGNAL NOISE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 10444286634     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Edenfeld, D.; Kahng, A.B.; Rodgers, M; Zorian, Y., "2003 Technology Roadmap for Semiconductors", IEEE Computer, vol. 37, pp. 47-56, IEEE Computer Society, New York-London, January 2004.
2. Graines, B. R., "Stochastic Computing Systems", Advances in Information Systems Science, vol. 2, pp. 37-172, Plenum Press, New York-London, 1969.