Arithmetic operators robust to multiple simultaneous upsets

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 289-297

  Lisboa C A L ^a   Carro, L ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROMAGNETIC NOISE; MULTIPLIERS; OPERANDS; RANDOM FAULTS;

COMPUTER SIMULATION; DIGITAL ARITHMETIC; ELECTROMAGNETISM; ERROR ANALYSIS; RANDOM PROCESSES; SPURIOUS SIGNAL NOISE;

TRANSISTORS;

EID: 24944549246     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347851     Document Type: Conference Paper

References (12)

1. Constantinescu, C., "Trends and Challenges in VLSI Circuit Reliability", IEEE Micro, vol. 23, no. 4, pp. 1419, IEEE Computer Society, New York-London, July/August 2003.
2. Edenfeld, D.; Kahng, A.B.; Rodgers, M.; Zorian, Y., "2003 Technology Roadmap for Semiconductors", IEEE Computer, vol. 37, pp. 47-56, IEEE Computer Society, New York-London, January 2004.
3. Semiconductor Industry Association. International Technology Roadmap for Semiconductors - ITRS 2003, http://public.itrs.net/Files/2003ITRS/Home2003.htm. Accessed in 02/27/2004.
4. Gaines, B. R., "Stochastic Computing Systems", Advances in Information Systems Science, vol. 2, pp. 37-172, Plenum Press, New York-London, 1969.
5. M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco, "Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study", IEEE Transactions on Nuclear Science, vol. 49, no. 3, pp. 1491-1495, IEEE Computer Society, New York-London, June 2002.
6. th Symposium on Integrated Circuits and Systems Design, SBCCI'02, pp. 9-13, IEEE Computer Society, Porto Alegre, September 2002.
7. Anghel, L. and Nicolaidis, M., "Cost Reduction and Evaluation of a Temporary Faults Detection Technique", in Proceedings of Design, Automation and Test in Europe Conference (DATE 2000), pp. 591-598, ACM, Paris, France, March 2000.
8. rd Symposium on Integrated Circuits and Systems Design (ICSD 2000), pp. 237-242, IEEE, Manaus, Brazil, September 2000.
9. Shivakumar, P. Kistler, M., Keckler, S. W., Burger, D., Alvisi, L., "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic", in Proceedings of the International Conference on Dependable Systems and Networks (DSN'02), 2002.
10. Lima, F., Carro, L. and Reis, R., "Techniques for Reconfigurable Logic Applications: Designing Fault Tolerant Systems into SRAM-based FPGAs", in Proceedings of the International Design Automation Conference, DAC 2003, pp. 650-655, ACM, New York, 2003.
11. Janer, C. L.; Quero, J. M.; Ortega, J. G. and Franquelo, L. G., "Fully Parallel Stochastic Computation Architecture", in IEEE Transactions on Signal Processing, vol. 44, no. 8, pp. 2110-2117, IEEE Computer Society, New York, 1996.
12. Lisbôa, C. and Carro, L., "An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets", in Proceedings of the 10th IEEE International On-Line Test Symposium, IOLTS 2004, pp. 180, IEEE Computer Society, New York, July 2004.