Scheduling of conditional process graphs for the synthesis of embedded systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 132-138

  Eles, Petru ^a,b   Kuchcinski, Krzysztof ^a   Peng, Zebo ^a   Doboli, Alexa ^b   Pop, Paul ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b POLITEHNICA UNIVERSITY OF TIMISOARA   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW ANALYSIS; EMBEDDED SYSTEMS; SCHEDULING;

DATA FLOW; FLOW OF CONTROL; GRAPH REPRESENTATION; PROCESS GRAPHS; PROCESS SCHEDULING; SHARED BUS; TARGET ARCHITECTURES;

FLOW GRAPHS;

EID: 0043196791     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655847     Document Type: Conference Paper

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