A low-noise 40-GS/s continuous-time bandpass ΔΣ ADC centered at 2 GHz for direct sampling receivers

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 5, 2007, Pages 1065-1074

  Chalvatzis, Theodoros ^a,b   Gagnon, Eric ^a,c   Repeta, Morris ^a,c   Voinigescu, Sorin P ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c NORTEL NETWORKS   (Canada)

Author keywords

Analog to digital converter; Continuous time; Delta sigma; Direct RF sampling; SiGe BiCMOS

Indexed keywords

CENTER FREQUENCY; DIRECT SAMPLING RECEIVERS; TRANSCONDUCTOR;

BANDWIDTH; BASE STATIONS; BICMOS TECHNOLOGY; DIGITAL FILTERS; SIGNAL RECEIVERS; SPURIOUS SIGNAL NOISE;

ANALOG TO DIGITAL CONVERSION;

EID: 34247368051     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.894794     Document Type: Conference Paper

References (23)

1. R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberga, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de Obaldia, and P. T. Balsara, "All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, Dec. 2004.
2. K. Muhammad, Y.-C. Ho, T. Mayhugh, C. M. Hungand, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M. C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, "A discrete time quadband GSM/GPRS receiver in a 90 nm digital CMOS process," in Proc. Custom IC Conf., San Jose, CA, Sep. 2005, pp. 809-812.
3. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge University Press, 2004.
4. A. Abidi, "Evolution of a software-defined radio receiver's RF front-end," in RFIC Dig. Papers, San Francisco, CA, Jun. 2006, pp. 27-30.
5. J. Cherry and W. Snelgrove, "Excess loop delay in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 4, pp. 376-389, Apr. 1999.
6. W. Gao and W. Snelgrove, "A 4 GHz fourth-order SiGe HBT bandpass AS modulator," in Proc. Symp. VLSI Circuits, Honolulu, HI, Jun. 1998, pp. 174-175.
7. A. Jayaraman, P. Asbeck, K. Nary, S. Beccue, and K.-C. Wang, "Bandpass delta-sigma modulator with 800 MHz center frequency," in GaAs IC Symp. Dig., Anaheim, CA, Oct. 1997, pp. 95-98.
8. A. E. Cosand, J. F. Jensen, H. C. Choe, and C. H. Fields, "IF-sampling fourth-order bandpass ΔΣ modulator for digital receiver applications," IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1633-1639, Oct. 2004.
9. T. Kaplan, J. Cruz-Albrecht, M. Mokhtari, D. Matthews, J. Jensen, and M. F. Chang, "A 1.3-GHz IF digitizer using a fourth-order continuous-time bandpass ΔΣ modulator," in Proc. Custom IC Conf., San Jose, CA, Sep. 2003, pp. 127-130.
10. J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, "Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1695-1702, Dec. 2002.
11. T. O. Dickson, R. Beerkens, and S. P. Voinigescu, "A 2.5-V, 45-Gb/s decision circuit using SiGe BiCMOS logic," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 994-1003, Apr. 2005.
12. R. Schreier and B. Zhang, "Delta-sigma modulators employing continuous-time circuitry," IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 43, no. 4, pp. 324-332, Apr. 1996.
13. O. Shoaei and W. M. Snelgrove, "Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass ΔΣ modulator," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 7, pp. 521-530, Jul. 1997.
14. R. Schaumann and M. E. V. Valkenburg, Design of Analog Filters. New York: Oxford University Press, 2001.
15. L. Breems and J. H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Boston, MA: Kluwer Academic, 2001.
16. G. N. Franklin, J. D. Powell, and A. Emami-Naieni, Feedback Control of Dynamic Systems, 4th ed. Upper Saddle River, NJ: Prentice Hall, 2002.
17. T. O. Dickson, K. H. K. Yau, T. Chalvatzis, A. M. Mangan, E. Laskin, R. Beerkens, P. Westergaard, M. Tazlauanu, M. T. Yang, and S. P. Voinigescu, "The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1830-1845, Aug. 2006.
18. S. Krishnan, D. Scott, Z. Griffith, M. Urteaga, Y. Wei, N. Parthasarathy, and M. Rodwell, "An 8-GHz continuous-time Δ - Σ analog-digital converter in an InP-based HBT technology," IEEE Trans. Microwave Theory Tech., vol. 51, no. 12, pp. 2555-2561, Dec. 2003.
19. H. Tao, L. Toth, and J. M. Khoury, "Analysis of timing jitter in bandpass sigma-delta modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 17, no. 8, pp. 991-1001, Aug. 1999.
20. R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Sel. Areas Commun., vol. 17, no. 4, pp. 539-550, Apr. 1999.
21. T. O. Dickson and S. P. Voinigescu, "Low-power circuits for a 10.7-to-86 Gb/s 80-Gb/s serial transmitter in 130-nm SiGe BiCMOS," in Dig. Symp. Compound Semiconductor IC, San Antonio, TX, Nov. 2006, pp. 235-238.
22. B. K. Thandri and J. Silva-Martinez, "A 63 dB, 75-mW bandpass RF ADC at 950 MHz using 3.8-GHz clock in 0.25-μm SiGe BiCMOS technology," IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 269-279, Feb. 2007.
23. X. Li, W.-M. Kuo, Y. Lu, and J. Cressler, "A 20 GS/sec analog-to- digital sigma-delta modulator in SiGe HBT technology," in Proc. Custom IC Conf., San Jose, CA, Sep. 2006, pp. 221-224.