A low power SRAM architecture based on segmented virtual grounding

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 256-261

  Sharifkhani, Mohammad ^a   Sachdev, Manoj ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Leakage reduction; Low power; SRAM; Static random access memory; Write power reduction

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS;

LEAKAGE REDUCTION; SEGMENTED VIRTUAL GROUNDING (SVGND);

STATIC RANDOM ACCESS STORAGE;

EID: 34247187362     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165635     Document Type: Conference Paper

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