Long-retention-time, high-speed DRAM array with 12-F2 twin cell for sub 1-V operation

IEICE Transactions on Electronics

Volumn E90-C, Issue 4, 2007, Pages 758-764

  Takemura, Riichiro ^a   Itoh, Kiyoo ^a   Sekiguchi, Tomonori ^a   Akiyama, Satoru ^a   Hanzawa, Satoru ^a   Kajigaya, Kazuhiko ^b   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

^b Elpida Memory Inc   (Japan)

Author keywords

Low voltage RAM; Plate driven cell; Retention time; Twin cell DRAM array; Write time

Indexed keywords

ELECTRIC BATTERIES; ELECTRIC CHARGE; THRESHOLD VOLTAGE;

LOW VOLTAGE RAM; PLATE-DRIVEN CELL; RETENTION TIME; TWIN-CELL DRAM ARRAY; WRITE TIME;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 34247097983     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e90-c.4.758     Document Type: Article

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