Concordant memory design using statistical integration for the billions-transistor era

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Akiyama, Satoru ^a   Sekiguchi, Tomonori ^a   Kajigaya, Kazuhiko ^b   Hanzawa, Satoru ^a   Takemura, Riichiro ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

^b Elpida Memory Inc   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844460848     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Microprocessor Circuit Design Forum, ISSCC Feb., 2004
2. J. Pineda de Gyvez et al., IEEE J. Solid-State Circuits, vol.39, No. 1, pp. 157-168, Jan., 2004.
3. G. A. M. Hurks, IEEE Trans. on Elec. Devices, vol. 39, pp. 2090-2098, 1992.
4. K. Itoh "VLSI Memory Chip Design", Springer.