A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-um cost-effective DRAM technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 188-189

  Noda, Hiromasa ^a   Miyatake, Shinichi ^b   Sekiguchi, Tomonori ^b   Takemura, Riichiro ^b   Sakata, Takeshi ^b   Saino, Kanta ^a   Kato, Yoshiki ^a   Kitamura, Eiji ^a   Kajigaya, Kazuhiko ^a  

^a Elpida Memory Inc   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

DRAM; High speed; Twin cell memory

Indexed keywords

ARRAYS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; MICROPROCESSOR CHIPS; SIGNAL INTERFERENCE; SPURIOUS SIGNAL NOISE;

GATE MEMORY-CELL-TRANSISTORS; HIGH-SPEED; LATCH-AMP TRANSFORMS; TWIN-CELL-MEMORY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 4544260532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Y. Sato, et al., Symp. an VLSI Circuit Digest of Technical Papers, pp.22-25, June, 1998.
2. I. Naritake, et al., ISSCC Digest of Technical Papers, pp. 420-421, February 1999.
3. T. Kimura, et al., ISSCC Digest of Technical Papers, pp. 416-417, February 1999.
4. Y. Agata, et al., ISSCC Digest of Technical Papers, pp. 392-393, February 2000.
5. O. Takahashi, et al., ISSCC Digest of Technical Papers, pp. 96-397, February 2000.
6. P. DeMone, et al., Symp. on VLSI Circuit Digest of Technical Papers, pp. 237-240, June 2001.
7. H. Pilo, et al., ISSCC Digest of Technical Papers, pp. 266-267, February 2003.
8. J. Barth et al., ISSCC Digest of Technical Papers, pp. 156-157, February 2002.
9. K. Saino, et al., IEDM Digest of Technical Papers, pp. 415-418, December 2003