A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 7, 2005, Pages 1482-1490

  Da Dalt, Nicola ^a   Thaller, Edwin ^a   Gregorius, Peter ^b   Gazsi, Lajos ^b  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Digital control; Digitally controlled oscillator; Inductors; Jitter; Phase locked loops

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC POTENTIAL; JITTER; MATHEMATICAL MODELS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS; WAVE PROPAGATION;

DIGITALLY CONTROLLED OSCILLATORS; FREQUENCY DETECTION; INDUCTORS; QUANTIZATION NOISE;

DIGITAL CONTROL SYSTEMS;

EID: 22544465884     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.847325     Document Type: Conference Paper

References (13)

1. N. Da Dalt, E. Thaller, P. Gregorius, and L. Gazsi, "A low jitter tripleband digital LC PLL in 130 nm CMOS," in Proc. ESSCIRC, Leuven, Belgium, Sep. 2004, pp. 371-374.
2. R. B. Staszewski et al., "All-digital phase domain TX frequency synthesizer for bluetooth radios in 0.13 um CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 272-273.
3. R. Walker, "Designing bang-bang PLLs for clock and data recovery in serial data transmission systems," in Phase-Locking in High Performance Systems, B. Razavi, Ed: IEEE Press, 2003.
4. K. B. Hardin, "Spread spectrum clock generation and associated method," U.S. Patent 5,488,627, Jan. 30, 1996.
5. M. Tiebout, "A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with a voltage controlled inductor," in Proc. ESSCIRC, Florence, Italy, 2002, pp. 789-802.
6. Y. M Greshishchev et al., "A fully integrated sige receiver IC for 10-Gb/s data rate," IEEE J. Solid State Circuits, vol. 35, no. 12, pp. 1949-1957, Dec. 2000.
7. Y. Choi et al., "Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 50, no. 11, pp. 775-783, Nov. 2003.
8. N. Da Dalt, "A design oriented study of the nonlinear dynamics of digital bang-bang PLLs," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005.
9. Q. Huang et al., "Speed optimization of edge triggered CMOS circuits for gigahertz single-phase clocks," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 456-465, Mar. 1996.
10. I. C. Hwang et al., "A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition," IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1574-1581, Oct. 2001.
11. Serial ATA II: Electrical Specifications, Revision 1.0 (2004, May 26). [Online]. Available: http://www.serialata.org
12. R. Van de Beek et al., "A 2.5 to 10 GHz clock multiplier unit with 0.22 ps RMS jitter in a 0.18 um CMOS technology," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 178-179.
13. M. Terrovitis et al., "A 3.2 to 4 GHz, 0.25 um CMOS frequency synthesizer for IEEE 802.11 a/b/g WLAN," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 98-99.