A mixed-signal decision-feedback equalizer that uses a look-ahead architecture

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 3, 1997, Pages 450-459

  Kajley, Ravinder S ^a,b,e,f   Hurst, Paul J ^a,c,g,h   Brown, James E C ^a,b,d,i,j  

^a Davis   (United States)

^b INTEL CORPORATION   (United States)

^c IEEE

^d Exar Corporation   (United States)

^e University of California ^*

^f UNIVERSITY OF CALIFORNIA   (United States)

^g Silicon Systems Inc   (United States)

^h UNIVERSITY OF CALIFORNIA   (United States)

ⁱ HEWLETT PACKARD COMPANY   (United States)

^j Precision Monolithics Inc   (United States)

more..

Author keywords

Adaptive equalizers; Decision feedback equalizers; Look ahead architecture; Magnetic disk recording; Mixed analog digital integrated circuits; Parallel processing

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL CIRCUITS; LINEAR INTEGRATED CIRCUITS; MAGNETIC DISK STORAGE; MAGNETIC RECORDING; PARALLEL PROCESSING SYSTEMS;

ADAPTIVE EQUALIZERS; DECISION FEEDBACK EQUALIZER; LOOK AHEAD; MIXED SIGNAL ARCHITECTURE;

EQUALIZERS;

EID: 0031103014     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.557648     Document Type: Article

References (35)

1. R. Philpott, R. Kertis, R. Richetta, T. Schmerbeck, and D. Schulte, "A 7 MB/sec (65 MHz) mixed-signal magnetic recording channel DSP using partial response with maximum likelihood detection," in CICC, 1993, pp. 10.4.1-10.4.4.
2. T. W. Matthews and R. R. Spencer, "An integrated analog CMOS Viterbi detector for digital magnetic recording," IEEE J. Solid-State Circuits, vol. 28, pp. 1294-1302, Dec. 1993.
3. R. G. Yamasaki, T. Pan, M. Palmer, and D. Browning, "A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor," in ISSCC, 1994, pp. 278-279.
4. K. Parsi et al., "A 200 Mb/s PRML read/write channel IC," in ISSCC, 1996, pp. 66-67.
5. J. Sonntag et al., "A high speed, low power PRML read channel device," IEEE Trans. Magn., vol. 31, pp. 1103-1108, Mar. 1995.
6. D. Welland et al., "Implementation of a digital read/write channel with EEPR4 detection," IEEE Trans. Magn., vol. 31, pp. 1180-1185, Mar. 1995.
7. P. K. Pai, A. D. Brewster, and A. A. Abidi, "A 160 MHz front-end IC for EPR-IV PRML magnetic storage read channels," in ISSCC, 1996, pp. 68-69.
8. J. W. Bergmans, "Density improvements in digital magnetic recording by decision feedback equalization," IEEE Trans. Magn., vol. M-22, pp. 157-162, May 1986.
9. J. M. Cioffi, W. L. Abbott, H. K. Thapar, C. M. Melas, and K. D. Fisher, "Adaptive equalization in magnetic-disk storage channels," IEEE Commun. Mag., pp. 14-29, Feb. 1990.
10. K. Han and R. Spencer, "Comparison of different detection techniques for digital magnetic recording channels," IEEE Trans. Magn., vol. 31, pp. 1128-1133, Mar. 1995.
11. P. S. Bednarz, N. P. Sands, C. S. Modlin, S. C. Lin, I. Lee, and J. M. Cioffi, "Performance evaluation of an adaptive RAM-DFE read channel," IEEE Trans. Magn. vol. 31, pp. 1121-1127, Mar. 1995.
12. K. D. Fisher, J. M. Cioffi, W. L. Abbott, P. S. Bednarz, and C. M. Melas, "An adaptive RAM-DFE for storage channels," IEEE Trans. Commun., vol 39, pp. 1559-1568, Nov. 1991.
13. P. Roo, R. R. Spencer, and P. J. Hurst, "Analog timing recovery architectures for PRML detectors," in Glabecom Conf. Rec., 1995, vol. 1, pp. 571-576.
14. J. Kovacs and K. McCall, "Hybrid phase lacked loop system for PRML disk drive read channels," in Symp VLSI Circuits, 1996, pp. 178-179.
15. N. P. Sands et al., "A 200 Mb/s analog DFE read channel," in ISSCC, 1996, pp. 72-73.
16. J. E. C. Brown, P. J. Hurst, L. Der. and I. Agi, "A comparison of analog DFE architectures for disk-drive applications," in Int. Symp. Circuits Systems, 1994, pp. 99-102.
17. U. Menzi and G. S. Moschytz, "Adaptive switched-capacitor filters based on the LMS algorithm," IEEE Trans. Circuits Syst. - I, vol. 40, pp. 929-942, Dec. 1993.
18. A. Shoval, D. A. Johns, and W. M. Snelgrove, "Comparison of DC offset effects in four LMS adaptive algorithms," IEEE Trans. Circuits Syst. - II, vol. 42, pp. 176-185, Mar. 1995.
19. J. E. Brown, P. Hurst, and L. Der, "A 35 Mb/s mixed-signal DFE for disk-drive applications," IEEE J. Solid-State Circuits, vol. 31, pp. 1258-1266, Sept. 1996.
20. B. Widrow and S. D. Stearns, Adaptive Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1985.
21. J. E. Brown, P. J. Hurst, and L. Der, "Design of an analog DFE for disk-dme applications," in Asilomar Conf. Signals, Systems. Comp., Oct. 1992, pp. 965-969.
22. M. L. Honig and D. G. Messerschmitt, Adaptive Filters. Boston, MA: Kluwer, 1984.
23. K. K Parhi, "Pipelining in algorithms with quantizer loops," IEEE Trans. Circuits Syst., pp. 745-754, July 1991.
24. G. Long, F. Ling, and J. G. Proakis, "The LMS algorithm with delayed coefficient adaption," IEEE Trans. Acoust., Speech. Signal Processing. vol. 37, pp. 1397-1405, Sept. 1989.
25. R. Gomez, M. Rofougaran, and A. A. Abidi, "A discrete-time analog signal processor for disk read channels," in ISSCC, Feb. 1993, pp. 212-213.
26. S. B. Lyle, G. Worstell, and R. R. Spencer, "An analog ducrete-time transversal filter in 2 μm CMOS," in Asilomar Conf. Signals. Systems Comp., Oct. 1992, pp. 970-974.
27. B. C. Rothenberg, S. H. Lewis, and P. J. Hurst, "A 20 MS/s switched-capacitor FIR filter using a transposed structure," IEEE J. Solid-State Circuits. vol. 30, pp. 1350-1356, Dec. 1995.
28. G. A. Veirman and R. G. Yamasaki, "Design of a bipolar 10-MHz programmable continuous-time 0.05° equiripple linear phase filter," IEEE J. Solid-State Circuits,vol. 27, pp. 324-331, Mar. 1992.
29. J. E. C. Brown and P. J. Hurst, "Adaptive continuous-time forward equalization for DFE-based read channels," in Asilomar Conf. Signals. Systems Comp., 1995, pp. 668-672.
30. D. Xu, Y. Song, and G. T. Uehara, "A 200-MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 μm CMOS," in ISSCC, 1996, pp. 74-75.
31. K. M. Ware, H.-S. Lee, and C. G. Sodini, "A 200-MHz CMOS phase-locked loop with dual phase detectors," IEEE J. Solid-State Circuits. vol. 24, pp. 1560-1568, Dec. 1989.
32. J. T. Wu and B. A. Wooley, "A 100-MHz pipelined CMOS comparator," IEEE J. Solid-State Circuits, vol. 23, pp. 1379-1385, Dec. 1988.
33. L. Der, S. Lewis, and P. Hurst, "A switched-capacitor differencing circuit with common-mode rejection for fully differential comparators," in Midwest Symp. Circuits Systems. Aug. 1993, pp. 911-914.
34. Y. Ji-Ren, I. Karlsson, and C. Svensson, "A true single-phase-clock dynamic CMOS circuit technique," IEEE J. Solid-State Circuits, vol. SC-22, pp. 899-901, Oct. 1987.
35. J. A. Bucklew, T. G. Kurtz, and W. A. Sethares, "Weak convergence and local stability properties of fixed step size recursive algorithms," IEEE Trans. Inform. Theory. vol. 30, pp. 966-978, May 1993.